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max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output general description the max9276a/max9280a gigabit multimedia serial link (gmsl) deserializers receive data from a gmsl serializer over 50 coax or 100 shielded twisted-pair (stp) cable and output deserialized data on the lvcmos outputs. the max9280a has hdcp content protection but other - wise is the same as the max9276a. the deserializers pair with any gmsl serializer capable of coax output including the max9293 hdmi/mhl serializer. when programmed for stp input they are backward compatible with any gmsl serializer. the audio channel supports l-pcm i 2 s stereo and up to eight channels of l-pcm in tdm mode. sample rates of 32khz to 192khz are supported with sample depth up to 32 bits. the embedded control channel operates at 9.6kbps to 1mbps in uart-to-uart and uart-to-i 2 c modes, and up to 1mbps in i 2 c-to-i 2 c mode. using the control channel, a c can program serializer, deserializer, and peripheral device registers at any time, independent of video timing, and manage hdcp operation (max9280a). two gpio ports are included, allowing display power- up and switching of the backlight among other uses. a continuously sampled gpi input supports touch-screen controller interrupt requests in display applications. for use with longer cables, the deserializers have a programmable cable equalizer. programmable spread spectrum is available on the parallel output. the seri- al input meets iso 10605 and iec 61000-4-2 esd standards. the core supply is 3.0v to 3.6v and the i/o supply is 1.7v to 3.6v. the devices are in lead-free, 56-pin, 8mm x 8mm tqfn and qfnd packages with exposed pad and 0.5mm lead pitch. applications high-resolution automotive navigation rear-seat infotainment megapixel camera systems beneits and features ideal for high-definition video applications ? works with low-cost 50 coax cable and fakra connectors or 100 stp ? 104mhz high-bandwidth mode supports 1920x720p/60hz display with 24-bit color ? equalization allows 15m cable at full speed ? up to 192khz sample rate and 32-bit sample depth for 7.1 channel hd audio ? audio clock from audio source or audio sink ? color lookup table for gamma correction ? cntl[3:0] control outputs multiple data rates for system flexibility ? up to 3.12gbps serial-bit rate ? 6.25mhz to 104mhz pixel clock ? 9.6kbps to 1mbps control channel in uart, mixed uart/i 2 c, or i 2 c mode with clock-stretch capability reduces emi and shielding requirements ? programmable spread spectrum reduces emi ? tracks spread spectrum on input ? high-immunity mode for maximum control- channel noise rejection peripheral features for system power-up and verification ? built-in prbs tester for ber testing of the serial link ? programmable choice of 8 default device addresses ? two dedicated gpio ports ? dedicated up/down gpi for touch-screen interrupt and other uses ? remote/local wake-up from sleep mode meets rigorous automotive and industrial requirements ? -40c to +105c operating temperature ? 8kv contact and 15kv air iso 10605 and iec 61000-4-2 esd protection 19-7639; rev 0; 1/16 ordering information and typical application circuit appear at end of data sheet. evaluation kit available downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 2 table of contents general description ............................................................................ 1 applications .................................................................................. 1 benefits and features .......................................................................... 1 absolute maximum ratings ...................................................................... 7 package thermal characteristics ................................................................. 7 dc electrical characteristics ..................................................................... 7 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 typical operating characteristics ................................................................ 15 pin configuration ............................................................................. 17 pin description ............................................................................... 17 functional diagram ........................................................................... 20 detailed description ........................................................................... 24 register mapping .................................................. ......................... 24 output bit map .................................................. ........................... 25 serial link signaling and data format ................................................... ........ 25 high-bandwidth mode .................................................. ..................... 28 audio channel ................................................... ........................... 28 audio channel input .................................................. .................... 28 audio channel output .................................................. ................... 31 additional mclk output for audio applications ................................................. 32 audio output timing sources .................................................. ............. 32 reverse control channel .................................................. ................... 32 control channel and register programming .................................................. .... 33 uart interface .................................................. ........................ 33 interfacing command-byte-only i 2 c devices with uart .................................................. ............................ 35 uart bypass mode .................................................. .................... 35 i 2 c interface .................................................. ............................. 36 start and stop conditions .................................................. ............. 36 bit transfer ................................................... ........................... 36 acknowledge .................................................. .......................... 37 slave address .................................................. ......................... 37 bus reset ................................................... ............................ 37 format for writing .................................................. ...................... 38 format for reading .................................................. ..................... 39 i 2 c communication with remote-side devices ................................................. 39 i 2 c address translation .................................................. .................... 39 gpo/gpi control .................................................. ......................... 40 downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 3 table of contents ( continued) line equalizer .................................................. ............................ 40 spread spectrum .................................................. ......................... 40 manual programming of the spread-spectrum divider .............................................. 40 hs/vs/de tracking ................................................... ....................... 41 serial input .................................................. .............................. 41 coax splitter mode ................................................... ....................... 41 cable-type configuration input .................................................. .............. 41 color lookup tables ................................................... ...................... 42 programming and verifying lut data ................................................... ...... 42 lut color translation .................................................. ................... 42 lut bit width ................................................... ......................... 42 recommended lut program procedure .................................................. .... 43 high-immunity reverse control-channel mode ................................................... . 44 sleep mode ................................................... ............................. 44 power-down mode .................................................. ........................ 44 configuration link ................................................... ........................ 44 link startup procedure ........................................................................ 45 high-bandwidth digital content protection (hdcp) .................................................. 47 encryption enable ................................................... ........................ 47 synchronization of encryption .................................................. ............... 47 repeater support .................................................. ......................... 47 hdcp authentication procedures ................................................................ 48 hdcp protocol summary ................................................... .................. 48 example repeater networktwo cs ................................................... ..... 52 detection and action upon new device connection ................................................ 55 notification of start of authentication and enable of enc ryption to downstream links ..................... 55 applications information ........................................................................ 56 self prbs test ................................................... .......................... 56 error checking .................................................. ........................... 56 err output .................................................. ............................. 56 auto error reset ................................................... ......................... 56 dual c control .................................................. .......................... 56 changing the clock frequency ................................................... .............. 56 fast detection of loss-of-synchronization ................................................... ..... 56 providing a frame sync (camera applications) ................................................... . 57 software programming of the device addresses ................................................... 57 3-level configuration inputs ................................................... ................ 57 downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 4 table of contents ( continued) configuration blocking .................................................. ..................... 57 compatibility with other gmsl devices .................................................. ....... 57 key memory .................................................. ............................. 57 hs/vs/de inversion .................................................. ....................... 57 ws/sck inversion .................................................. ........................ 57 gpios .................................................. .................................. 58 staggered parallel outputs ................................................... ................. 58 internal input pulldowns .................................................. .................... 58 choosing i 2 c/uart pullup resistors .................................................. ......... 58 ac-coupling .................................................. ............................. 58 selection of ac-coupling capacitors ................................................... ......... 58 power-supply circuits and bypassing .................................................. ......... 58 power-supply table .................................................. ....................... 59 cables and connectors .................................................. .................... 59 board layout ................................................... ............................ 60 esd protection .................................................. ........................... 60 typical application circuit ...................................................................... 69 chip information .............................................................................. 69 package information .......................................................................... 69 ordering information .......................................................................... 69 revision history .............................................................................. 70 downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 5 list of figures figure 1. control-channel output parameters ...................................................... 21 figure 2. test circuit for differential input measurement .............................................. 21 figure 3. test circuit for single-ended input measurement ............................................ 22 figure 4. worst-case pattern output ............................................................. 22 figure 5. i 2 c timing parameters ................................................................. 22 figure 6. parallel clock output requirements ...................................................... 22 figure 7. output rise-and-fall times ............................................................. 23 figure 8. deserializer delay ..................................................................... 23 figure 9. gpi-to-gpo delay .................................................................... 23 figure 10. lock time .......................................................................... 24 figure 11. power-up delay ..................................................................... 24 figure 12. output i 2 s timing parameters .......................................................... 24 figure 13. 24-bit mode serial-data format ......................................................... 26 figure 14. 32-bit mode serial-data format ......................................................... 27 figure 15. high-bandwidth mode seria-data format ................................................. 27 figure 16. audio channel input format ............................................................ 28 figure 17. 8-channel tdm (24-bit samples, padded with zeros ) ....................................... 30 figure 18. 6-channel tdm (24-bit samples, no padding) ............................................. 30 figure 19. stereo i 2 s (24-bit samples, padded with zeros) ........................................... 30 figure 20. stereo i 2 s (16-bit samples, no padding) ................................................. 31 figure 21. audio channel output format .......................................................... 31 figure 22. gmsl uart protocol for base mode .................................................... 33 figure 23. gmsl uart data format for base mode ................................................. 34 figure 24. sync byte (0x79) ..................................................................... 34 figure 25. ack byte (0xc3) ..................................................................... 34 figure 26. format conversion between gmsl uart and i 2 c with register address (i2cmethod = 0) ........ 34 figure 27. format conversion between gmsl uart and i 2 c with register address (i2cmethod = 1) ........ 35 figure 28. start and stop conditions .......................................................... 36 figure 29. bit transfer ......................................................................... 36 figure 30. acknowledge ........................................................................ 37 figure 31. slave address ....................................................................... 37 figure 32. format for i 2 c write .................................................................. 38 figure 33. format for write to multiple registers .................................................... 38 figure 34. format for i 2 c read .................................................................. 39 figure 35. 2:1 coax splitter connection diagram ..................................................... 41 figure 36. coax connection diagram .............................................................. 41 figure 37. lut dataflow ........................................................................ 43 figure 38. state diagram ....................................................................... 46 downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 6 list of tables table 1. device address defaults (register 0x00, 0x01) .............................................. 25 table 2. output map ........................................................................... 26 table 3. data-rate selection table ............................................................... 28 table 4. maximum audio ws frequency (khz) for various pclkout f requencies ......................... 29 table 5. f src settings ........................................................................ 32 table 6. i 2 c bit-rate ranges ................................................................... 39 table 7. cable equalizer boost levels ............................................................. 40 table 8. output spread ........................................................................ 40 table 9. modulation coefficients and maximum sdiv se ttings ......................................... 40 table 10. configuration input map ................................................................. 41 table 11. pixel data format ..................................................................... 42 table 12. reverse control-channel modes ......................................................... 44 table 13. fast high-immunity mode requirements ................................................... 44 table 14. startup procedure for video-display applications ........................................... 45 table 15. startup procedure for image-sensing appli cations (cds = high) ............................... 46 table 16. startup, hdcp authentication, and normal operatio n (deserializer is not a repeater)first part of the hdcp authentication protocol ................................................................... 48 table 17. link integrity check (normal)performed every 128 f rames after encryption is enabled ........... 50 table 18. optional enhanced link integrity checkperforme d every 16 frames after encryption is enabled .... 51 table 19. hdcp authentication and normal operation (one repe ater, two cs)first and second parts of the hdcp authentication protocol ................................................................... 52 table 20. max9276a/max9280a feature compatibility .............................................. 57 table 21. staggered output delay ................................................................ 58 table 22. iovdd current simulation results ....................................................... 59 table 23. additional supply current from hdcp (max9280a only) ..................................... 59 table 24. suggested connectors and cables for gmsl ............................................... 59 table 25. register table (see table 26 ) ........................................................... 61 table 26. hdcp register table (max9280a only, see table 25 ) ....................................... 67 list of figures ( continued) figure 39. example network with one repeater and tw o cs (tx = gmsl serializers, rx = deserializers) ..... 52 figure 40. human body model esd test circuit ..................................................... 60 figure 41. iec 61000-4-2 contact discharge esd test circuit ......................................... 60 figure 42. iso 10605 contact discharge esd test circuit ............................................ 60 downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 7 dc electrical characteristics (v avdd = v dvdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), ep connected to pcb ground (gnd), t a = -40c to +105c, unless otherwise noted. typical values are at v avdd = v dvdd = v iovdd = 3.3v, t a = +25c.)(note 3) note 2: package thermal resistances were obtained using the method described in jedec specification jesd51- 7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . avdd to ep ..........................................................-0.5v to +3.9v dvdd to ep .........................................................-0.5v to +3.9v iovdd to ep ........................................................-0.5v to +3.9v in+, in- to ep .......................................................-0.5v to +1.9v all other pins to ep ............................-0.5v to (v iovdd + 0.5v) in+, in- short circuit to ground or supply ...............continuous continuous power dissipation (t a = +70c) tqfn (derate 47.6mw/c above +70c)...............3809.5mw qfnd (derate 4.2mw/c above +70c). ..................3418mw junction temperature ......................................................+150c storage temperature ........................................ -65c to +150c lead temperature (soldering, 10s) ................................. +300c soldering temperature (reflow) .......................................+260c stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (note 1) package thermal characteristics (note 2) tqfn junction-to-ambient thermal resistance ( ja ) ..........21c/w junction-to-case thermal resistance ( jc ) .................1c/w qfnd junction-to-ambient thermal resistance ( ja )....23.4c/w junction-to-case thermal resistance ( jc )..........1.6c/w absolute maximum ratings note 1: ep connected to pcb ground. parameter symbol conditions min typ max units single-ended inputs (add_, him, i2csel, gpi, pwdn , ms) high-level input voltage v ih1 0.65 x v iovdd v low-level input voltage v il1 0.35 x v iovdd v input current i in1 v in = 0v to v iovdd -10 +20 a three-level logic inputs (bws, cx/tp) high-level input voltage v ih 0.7 x v iovdd v low-level input voltage v il 0.3 x v iovdd v mid-level input current i inm (note 4) -10 10 a input current i in -150 150 a single-ended outputs (ws, sck, sd, dout_, cntl_, intout, pclkout) high-level output voltage v oh1 i out = -2ma dcs = 0 v iovdd - 0.3 v dcs = 1 v iovdd - 0.2 low-level output voltage v ol1 i out = 2ma dcs = 0 0.3 v dcs = 1 0.2 downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 8 dc electrical characteristics (continued) (v avdd = v dvdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), ep connected to pcb ground (gnd), t a = -40c to +105c, unless otherwise noted. typical values are at v avdd = v dvdd = v iovdd = 3.3v, t a = +25c.) (note 3) parameter symbol conditions min typ max units output short-circuit current i os dout_ v o = 0v, dcs = 0 v iovdd = 3.0v to 3.6v 15 25 39 ma v iovdd = 1.7v to 1.9v 3 7 13 v o = 0v, dcs = 1 v iovdd = 3.0v to 3.6v 20 35 63 v iovdd = 1.7v to 1.9v 5 10 21 pclkout v o = 0v, dcs = 0 v iovdd = 3.0v to 3.6v 15 33 50 v iovdd = 1.7v to 1.9v 5 10 17 v o = 0v, dcs = 1 v iovdd = 3.0v to 3.6v 30 54 97 v iovdd = 1.7v to 1.9v 9 16 32 open-drain inputs/outputs (gpio0, gpio1, rx/sda, tx/scl, err , lock) high-level input voltage v ih2 0.7 x v iovdd v low-level input voltage v il2 0.3 x v iovdd v input current i in2 (note 5) rx/sda, tx/scl -100 +5 a lock, err , gpio_ -80 +5 low-level output voltage v ol2 i out = 3ma v iovdd = 1.7v to 1.9v 0.4 v v iovdd = 3.0v to 3.6v 0.3 input capacitance c in each pin (note 6) 10 pf outputs for reverse control channel (in+, in-) differential high output peak voltage (v in +) - (v in -) v rodh forward channel disabled, figure 1 legacy reverse control-channel mode 30 60 mv high-immunity mode 50 100 differential low output peak voltage (v in +) - (v in -) v rodl forward channel disabled, figure 1 legacy reverse control-channel mode -60 -30 mv high-immunity mode -100 -50 single-ended high output peak voltage v rosh forward channel disabled legacy reverse control-channel mode 30 60 mv high-immunity mode 50 100 single-ended low output peak voltage v rosl forward channel disabled legacy reverse control-channel mode -60 -30 mv high-immunity mode -100 -50 downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 9 dc electrical characteristics (continued) (v avdd = v dvdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), ep connected to pcb ground (gnd), t a = -40c to +105c, unless otherwise noted. typical values are at v avdd = v dvdd = v iovdd = 3.3v, t a = +25c.) (note 3) parameter symbol conditions min typ max units differential inputs (in+, in-) differential high input threshold (peak) voltage (v in +) - (v in -) v idh(p) figure 2 activity detector medium threshold, (0x0b d[6:5] = 01) 60 mv activity detector low threshold, (0x0b d[6:5] = 00) 47.5 differential low input threshold (peak) voltage (v in +) - (v in -) v idl(p) figure 2 activity detector medium threshold, (0x0b d[6:5] = 01) -60 mv activity detector medium threshold, (0x0b d[6:5] = 00) -47.5 input common-mode voltage ((v in +) + (v in -))/2 v cmr 1 1.3 1.6 v differential input resistance (internal) r in 80 100 130 single-ended inputs (in+, in-)single-ended high input threshold (peak) voltage (figure 3) v ish(p) activity detector medium threshold, (0x0b d[6:5] = 01) 43 mv activity detector low threshold, (0x0b d[6:5] = 00) 33 single-ended low input threshold (peak) voltage (figure 3) v isl(p) activity detector medium threshold, (0x0b d[6:5] = 01) -43 mv activity detector medium threshold, (0x0b d[6:5] = 00) -33 input resistance (internal) r i 40 50 65 power supply total supply current (avdd + dvdd + iovdd) (note 7) (worst-case-pattern, figure 4) i wcs bws = low, f pclkout = 16.6mhz 2% spread active c l = 5pf 131 164 ma c l = 10pf 136 169 spread spectrum disabled c l = 5pf 122 153 c l = 10pf 127 158 bws = low, f pclkout = 33.3mhz 2% spread active c l = 5pf 144 179 c l = 10pf 153 189 spread spectrum disabled c l = 5pf 133 167 c l = 10pf 142 177 bws = low, f pclkout = 66.6mhz 2% spread active c l = 5pf 175 216 c l = 10pf 190 233 spread spectrum disabled c l = 5pf 159 197 c l = 10pf 174 214 downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 10 dc electrical characteristics (continued) (v avdd = v dvdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), ep connected to pcb ground (gnd), t a = -40c to +105c, unless otherwise noted. typical values are at v avdd = v dvdd = v iovdd = 3.3v, t a = +25c.) (note 3) parameter symbol conditions min typ max units total supply current (avdd + dvdd + iovdd) (note 7) (worst-case-pattern, figure 4) i wcs bws = low, f pclkout = 104mhz 2% spread active c l = 5pf 212 255 ma c l = 10pf 234 278 spread spectrum disabled c l = 5pf 190 228 c l = 10pf 212 251 bws = mid, f pclkout = 36.6mhz 2% spread active c l = 5pf 154 191 c l = 10pf 164 203 spread spectrum disabled c l = 5pf 143 177 c l = 10pf 154 189 bws = mid, f pclkout = 104mhz 2% spread active c l = 5pf 231 277 c l = 10pf 257 305 spread spectrum disabled c l = 5pf 209 249 c l = 10pf 234 277 sleep mode supply current i ccs 70 265 a power-down current i ccz pwdn = gnd 20 195 a esd protection in+, in- (note 8) v esd human body model, r d = 1.5k, c s = 100pf 8 kv iec 61000-4-2, r d = 330, c s = 150pf contact discharge 10 air discharge 12 iso 10605, r d = 2k, c s = 330pf contact discharge 10 air discharge 20 all other pins (note 9) v esd human body model, r d = 1.5k, c s = 100pf 4 kv downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 11 ac electrical characteristics (v avdd = v dvdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), ep connected to pcb ground (gnd), t a = -40c to +105c, unless otherwise noted. typical values are at v avdd = v dvdd = v iovdd = 3.3v, t a = +25c.) (note 10) parameter symbol conditions min typ max units parallel clock output (pclkout) clock frequency f pclkout bws = low, drs = 1 8.33 16.66 mhz bws = low, drs = 0 16.66 104 bws = mid, drs = 1 18.33 36.66 bws = mid, drs = 0 36.66 104 bws = high, drs = 1 6.25 12.5 bws = high, drs = 0 12.5 78 clock duty cycle dc t high /t t or t low /t t (note 6) 40 50 60 % clock jitter t j period jitter, peak-to-peak, spread off, 3.12gbps, prbs pattern, ui = 1/f pclkout (note 6) 0.05 ui i 2 c/uart port timing i 2 c/uart bit rate 9.6 1000 kbps output rise time t r 30% to 70%, c l = 10pf to 100pf, 1k pullup to v iovdd 20 150 ns output fall time t f 70% to 30%, c l = 10pf to 100pf, 1k pullup to v iovdd 20 150 ns i 2 c timing (figure 5) scl clock frequency f scl low f scl range: (i2cmstbt = 010, i2cslvsh = 10) 9.6 100 khz mid f scl range: (i2cmstbt 101, i2cslvsh = 01) > 100 400 high f scl range: (i2cmstbt = 111, i2cslvsh = 00) > 400 1000 start condition hold time t hd:sta f scl range low 4.0 s mid 0.6 high 0.26 low period of scl clock t low f scl range low 4.7 s mid 1.3 high v iovdd = 1.7v to < 3v (note 11) 0.6 v iovdd = 3.0v to 3.6v 0.5 high period of scl clock t high f scl range low 4.0 s mid 0.6 high 0.26 repeated start condition setup time t su:sta f scl range low 4.7 s mid 0.6 high 0.26 downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 12 ac electrical characteristics (continued) (v avdd = v dvdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), ep connected to pcb ground (gnd), t a = -40c to +105c, unless otherwise noted. typical values are at v avdd = v dvdd = v iovdd = 3.3v, t a = +25c.) (note 10) parameter symbol conditions min typ max units data hold time t hd:dat f scl range low 0 s mid 0 high 0 data setup time t su:dat f scl range low 250 s mid 100 high 50 setup time for stop condition t su:sto f scl range low 4.0 s mid 0.6 high 0.26 bus free time t buf f scl range low 4.7 s mid 1.3 high 0.5 data valid time t vd:dat f scl range low 3.45 s mid 0.9 high v iovdd = 1.7v to < 3v (note 12) 0.55 v iovdd = 3.0v to 3.6v 0.45 data valid acknowledge time t vd:ack f scl range low 3.45 s mid 0.9 high v iovdd = 1.7v to < 3v (note 13) 0.55 v iovdd = 3.0v to 3.6v 0.45 pulse width of spikes suppressed t sp f scl range low 50 ns mid 50 high 50 capacitive load each bus line c b 100 pf switching characteristics pclkout rise-and-fall time (note 6, figure 6) t r , t f 20% to 80%,v iovdd = 1.7v to 1.9v dcs = 1, c l = 10pf 0.4 2.2 ns dcs = 0, c l = 5pf 0.5 2.8 20% to 80%,v iovdd = 3.0v to 3.6v dcs = 1, c l = 10pf 0.25 1.8 dcs = 0, c l = 5pf 0.3 2.0 parallel data rise-and-fall time (note 6, figure 7) t r , t f 20% to 80%,v iovdd = 1.7v to 1.9v dcs = 1, c l = 10pf 0.5 3.1 ns dcs = 0, c l = 5pf 0.6 3.8 20% to 80%,v iovdd = 3.0v to 3.6v dcs = 1, c l = 10pf 0.3 2.2 dcs = 0, c l = 5pf 0.4 2.4 downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 13 ac electrical characteristics (continued) (v avdd = v dvdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), ep connected to pcb ground (gnd), t a = -40c to +105c, unless otherwise noted. typical values are at v avdd = v dvdd = v iovdd = 3.3v, t a = +25c.) (note 10) parameter symbol conditions min typ max units deserializer delay t sd figure 8 (notes 6, 14) spread spectrum enabled 6960 bits spread spectrum disabled 2160 reverse control-channel output rise time t r no forward channel data transmission, figure 1 (note 6) 180 400 ns reverse control-channel output fall time t f no forward channel data transmission, figure 1 (note 6) 180 400 ns gpi-to-gpo delay t gpio deserializer gpi to serializer gpo (cable delay not included), figure 9 350 s lock time t lock (figure 10) spread spectrum enabled 3 ms spread spectrum disabled 2 power-up time t pu (figure 11) 8 ms i 2 s/tdm output timing (note 6) ws jitter tj ws t ws = 1/f ws , (cycle-to-cycle), rising-to-falling edge or falling-to- rising edge f ws = 48khz or 44.1khz 1.2e-3 x t ws 1.5e-3 x t ws ns f ws = 96khz 1.6e-3 x t ws 2e-3 x t ws f ws = 192khz 1.6e-3 x t ws 2e-3 x t ws sck jitter (2-channel i 2 s) tj sck1 t sck = 1/f sck , (cycle-to-cycle), rising-to-rising edge n sck = 16 bits, f sck = 48khz or 44.1khz 13e-3 x t sck 16e-3 x t sck ns n sck = 24 bits, f ws = 96khz 39e-3 x t sck 48e-3 x t sck n sck = 32 bits, f ws = 192khz 0.1 x t sck 0.13 x t sck sck jitter (8-channel tdm) tj sck2 t sck = 1/f sck , (cycle-to-cycle), rising-to-rising edge n sck = 16 bits, f ws = 48khz or 44.1khz 52e-3 x t sck 64e-3 x t sck ns n sck = 24 bits, f ws = 96khz 156e-3 x t sck 192e-3 x t sck n sck = 32 bits, f ws = 192khz 0.4 x t sck 0.52 x t sck audio skew relative to video t ask video and audio synchronized 3 x t ws 4 x t ws s sck, sd, ws rise-and-fall time t r , t f 20% to 80% c l = 10pf, dcs = 1 0.3 3.1 ns c l = 5pf, dcs = 0 0.4 3.8 downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 14 note 3: limits are 100% production tested at t a = +25c. limits over the operating temperature range are guaranteed by design and characterization, unless otherwise noted. note 4: to provide a mid level, leave the input open, or, if driven, put driver in high impedance. high-imp edance leakage current must be less than 10a. note 5: i in min due to voltage drop across the internal pullup resistor. note 6: not production tested. guaranteed by design. note 7: hdcp not enabled (max9280a only). iovdd current is not production tested. see table 23 for additional supply current when hdcp is enabled note 8: specified pin to ground. note 9: specified pin to all supply/ground. note 10: not production tested, guaranteed by bench characterization. note 11: the i 2 c bus standard t low (min) = 0.5s. note 12: the i 2 c bus standard t vd:dat (max) = 0.45s. note 13: . the i 2 c bus standard t vd:ack (max) = 0.45s. note 14: measured in serial link bit times. bit time = 1/(30 x f pclkin ) for bws = 0 or open. bit time = 1/(40 x f pclkin ) for bws = 1. ac electrical characteristics (continued) (v avdd = v dvdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), ep connected to pcb ground (gnd), t a = -40c to +105c, unless otherwise noted. typical values are at v avdd = v dvdd = v iovdd = 3.3v, t a = +25c.) (note 10) parameter symbol conditions min typ max units sd, ws valid time before sck (2-channel i 2 s) t dvb1 t sck = 1/f sck (figure 12) 0.20 x t sck 0.5 x t sck ns sd, ws valid time after sck (2-channel i 2 s) t dva1 t sck = 1/f sck (figure 12) 0.20 x t sck 0.5 x t sck ns sd, ws valid time before sck (8-channel tdm) t dvb2 t sck = 1/f sck (figure 12) 0.20 x t sck 0.5 x t sck ns sd, ws valid time after sck (8-channel tdm) t dva2 t sck = 1/f sck (figure 12) 0.20 x t sck 0.5 x t sck ns downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output maxim integrated 15 www.maximintegrated.com typical operating characteristics (v avdd = v dvdd = v iovdd = 3.3v, t a = +25c, unless otherwise noted.) supply current vs. pclkout frequency (bws = 0) max9726a toc01 pclkout frequency (mhz) supply current (ma) 65 75 85 95 45 55 35 25 15 130 140 150 160 170 180 190 200120 5 105 prbs on, ss off,coax mode eq on eq off supply current vs. pclkout frequency (bws = 1) max9726a toc02 pclkout frequency (mhz) supply current (ma) 50 65 35 20 130 140 150 160 170 180 190120 5 80 prbs on, ss off,coax mode eq on eq off supply current vs. pclkout frequency (bws = open) max9726a toc03 pclkout frequency (mhz) supply current (ma) 60 95 75 45 30 140 150 160 180170 190 200 210130 15 105 prbs on, ss off,coax mode eq on eq off supply current vs. pclkout frequency (bws = 1) max9726a toc05 pclkout frequency (mhz) supply current (ma) 50 65 35 20 140 150 160 180170 190 200 210130 5 80 prbs on, eq on,coax mode ss on ss off supply current vs. pclkout frequency (bws = 0) max9726a toc04 pclkout frequency (mhz) supply current (ma) 65 75 85 95 45 55 35 25 15 130 140 150 160 170 180 190 200 210 220120 5 105 prbs on, eq on,coax mode ss on ss off supply current vs. pclkout frequency (bws = open) max9726a toc06 pclkout frequency (mhz) supply current (ma) 75 90 60 45 30 150 160 170 180 190 200 210 220 230 240140 15 105 prbs on, eq on,coax mode ss on ss off downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output maxim integrated 16 www.maximintegrated.com typical operating characteristics (continued) (v avdd = v dvdd = v iovdd = 3.3v, t a = +25c, unless otherwise noted.) maximum pclkout frequency vs. coax cable length (ber 10 -10 ) max9726a toc09 cable length (m) frequency (mhz) 10 15 20 5 0 25 ber can be as low as 10 -12 for cable lengths less than 15m -70 -60 -40 -20 -10 10 -90 optimum pe/eq no pe, 10.7db eq output power spectrum vs. pclkout frequency (various spread) max9726a toc07 pclkout frequency (mhz) output power (dbm) 34.0 33.0 33.5 35.0 34.5 32.5 32.0 31.5 -80 -70 -60 -50 -40 -30 -20 -10 0 10 -90 31.0 35.5 0% spread 4% spread f pclkout = 33.3mhz 2% spread output power spectrum vs. pclkout frequency (various spread) max9726a toc08 pclkout frequency (mhz) output power (dbm) 68 66 67 70 69 65 64 63 62 71 0% spread 4% spread f pclkout = 66.7mhz 2% spread -80 -70 -60 -50 -40 -30 -20 -10 0 10 -90 downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 17 pin description pin coniguration pin name function 1 enable active-low parallel output-enable input with internal pulldown to ep. set enable = low to enable pclkout dout_ and cntl_ outputs. set enable = high to put pclkout, dout_ and cntl_ into high impedance. 2 intout/add2 a/v status register interrupt output/address selection input with internal pulldown to ep. functions as add2 input at power-up or when resuming from power-down mode ( pwdn = low), and switches to intout output automatically after power-up. add2: bit value is latched at power-up or when resuming from power-down mode ( pwdn = low). see table 1. connect intout/add2 to iovdd with a 30k resistor to set high or leave open to set low. intout: indicates new data in the a/v status registers. intout is reset when the a/v status register s are read. 3 gpi general-purpose input with internal pulldown to ep. the serializer gpo (or int) output follows gp i. 4 i2csel i 2 c select. control-channel interface protocol select input with internal pulldown to ep. set i2csel = high to select i 2 c interface. set i2csel = low to select uart interface. 5 gpio0 open-drain, general-purpose input/output with internal 60k pullup to iovdd top view max9276amax9280a tqfn/qfnd 25 2615 16 17 18 19 20 21 22 23 24 dout26 + dout25 27 28 iovdd dout24 rx/sda tx/scl pwdn err lock ws sck sd/him dout28/cntl2 dout27/cntl1 54 53 52 51 50 49 48 47 46 45 44 43 1 2 345 67 89 10 11 12 13 14 dout0 dout1 56 55 cx /t p *connect ep to ground plane avdd ep dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 iovdd dout10 gpio1 cntl3/add1cntl0/add0 dvdd ms in- in+ avdd bws gpio0 i2csel gpi intout/add2 enable 36 35 34 33 32 31 30 29 40 39 38 37 pclkout dout15 dout14 dout13 42 41 dout12 dout11dout23 dout22 dout21 dout20/de dout19/vs dout18/hs dout17 dout16 downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 18 pin description (continued) pin name function 6 bws three-level bus width select input. set bws to the same level on both sides of the serial link. set bws = low for 24 bit mode. set bws = high for 32-bit mode. set bws = open for high-bandwidth mode. 7, 55 avdd 3.3v analog power supply. bypass avdd to ep with 0.1f and 0.001f capacitors as close as possible to the device with the smaller capacitor closest to avdd. 8 in+ noninverting coax/twisted-pair serial input 9 in- inverting coax/twisted-pair serial input 10 ms mode select with internal pulldown to ep. set ms = low, to select base mode. set ms = high to select the bypass mode. 11 cntl3/add1 auxiliary control signal output/address selection input with internal pulldown to ep. functions as add1 input at power-up or when resuming from power-down mode ( pwdn = low), and switches to cntl3 output automatically after power-up.add1: bit value is latched at power-up or when resuming from power-down mode ( pwdn = low). see table 1. connect cntl3/add1 to iovdd with a 30k resistor to set high or leave open to set low. cntl3: used only in high-bandwidth mode (bws = open). cntl3 not encrypted when hdcp is enabled (max9280a only). 12 gpio1 open-drain, general-purpose input/output with internal 60k pullup to iovdd 13 dvdd 3.3v digital power supply. bypass dvdd to ep with 0.1f and 0.001f capacitors as close as possible to the device with the smaller value capacitor closest to dvdd. 14 cntl0/add0 auxiliary control signal output/address selection input with internal pulldown to ep. functions as add0 input at power-up or when resuming from power-down mode ( pwdn = low), and switches to cntl0 output automatically after power-up.add0: bit value is latched at power-up or when resuming from power-down mode ( pwdn = low). see table 1. connect cntl0/add0 to iovdd with a 30k resistor to set high or leave open to set low. cntl0: used only in high-bandwidth mode (bws = open). cntl0 not encrypted when hdcp is enabled (max9280a only ). 15 rx/sda uart receive/i 2 c serial-data input/output with internal 30k pullup to iovdd. function is determined by the state of i2csel at power-up. rx/sda has an open-drain driver and requires a pullup resistor. rx: input of the serializers uart. sda: data input/output of the serializers i 2 c master/slave. 16 tx/scl uart transmit/i 2 c serial-clock input/output with internal 30k pullup to iovdd. function is determined by the state of i2csel at power-up. tx/scl has an open-drain driver and requires a pullup resistor. tx: output of the serializers uart. scl: clock input/output of the serializers i 2 c master/slave. 17 pwdn active-low, power-down input with internal pulldown to ep. set pwdn low to enter power-down mode to reduce power consumption. 18 err error output. open-drain data error detection and/or correction indication output with internal 30k pullup to iovdd. err is high when pwdn is low 19 lock open-drain lock output with internal 30k pullup to iovdd. lock = high indicates that plls are locked with correct serial-word-boundary alignment. lock = low indicates that plls are not locked or an incorrect serial-word-boundary alignment. lock is high when pwdn = low. downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 19 pin description (continued) pin name function 20 ws i 2 s/tdm word-select input/output. powers up as an i 2 s output (deserializer-provided clock). set audiomode bit = 1 to change ws to an input with internal pulldown to gnd and supply ws externally (system provided clock). 21 sck i 2 s/tdm serial-clock input/output. powers up as an i 2 s output (deserializer-provided clock). set audiomode bit = 1 to change sck to an input with internal pulldown to gnd and supply ws externally (system provided clock). 22 sd/him i 2 s/tdm serial-data output/high-immunity mode input. functions as him input with internal pulldown to ep at power-up or when resuming from power-down mode ( pwdn = low), and switches to sd output automatically after power-up. him: default highimm bit value is latched at power-up or when resuming from power-down mode ( pwdn = low) and is active-high. connect sd/him to iovdd with a 30k resistor to set high or leave open to set low. highimm can be programmed to a different value after power-up. highimm in the serializer must be set to the same value. sd: disable i 2 s/tdm encoding to serial data to use sd as an additional control/data output valid on the selected edge of pclkout. encrypted when hdcp is enabled (max9280a only). 23 dout28/cntl2 parallel data/auxiliary control signal output valid on the selected edge of pclkout. dout28/cntl2 remains high impedance in 24-bit mode (bws = low) dout28 used only in 32-bit mode (bws = high). dout28 not encrypted when hdcp is enabled (max9280a only). cntl2 used only in high-bandwidth mode (bws = open). cntl2 not encrypted when hdcp is enabled (max9280a only). 24 dout27/cntl1 parallel data/auxiliary control signal output valid on the selected edge of pclkout. dout27/cntl1 remains high impedance in 24-bit mode (bws = low) dout27 used only in 32-bit mode (bws = high). dout27 not encrypted when hdcp is enabled (max9280a only). cntl1 used only in high-bandwidth mode (bws = open). cntl1 not encrypted when hdcp is enabled (max9280a only) 25, 26, 28C31 dout[26:21] parallel data outputs valid on the selected edge of pclkout. encrypted when hdcp is enabled (max9280a only). dout[26:21] used only in 32-bit and high-bandwidth modes (bws = high or open). dout[26:21] remains high-impedance in 24-bit mode. 27, 44 iovdd i/o supply voltage. 1.8v to 3.3v logic i/o power supply. bypass iovdd to ep with 0.1f and 0.001f capacitors as close as possible to the device with the smallest value capacitor closest to iovdd. 32 dout20/de parallel data/device enable output valid on the selected edge of pclkout. defaults to parallel data output on power-up. device enable output when hdcp is enabled (max9280a only) or when in high-bandwidth mode (bws = open). 33 dout19/vs parallel data/vertical sync output valid on the selected edge of pclkout. defaults to parallel data output on power-up. vertical sync output when hdcp is enabled (max9280a only) or when in high-bandwidth mode (bws = open). 34 dout18/hs parallel data/horizontal sync output valid on the selected edge of pclkout. defaults to parallel dat a output on power-up. horizontal sync output when hdcp is enabled (max9280a only) or when in high-bandwidth mode (bws = open). downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 20 pin description (continued)functional diagram pin name function 35, 36, 38C43, 45C54 dout[17:0] parallel data outputs valid on the selected edge of pclkout. encrypted when hdcp is enabled (max9280a only) 37 pclkout parallel clock output used for dout[28:0]. latches parallel data into the input of another de vice. 56 cx/tp three-level coax/twisted pair select input. see table 10 for function. ep exposed pad. ep is internally connected to device ground. must connect ep to the pcb ground plane through an array of vias for proper thermal and electrical performance. 8b/10 b or 9b10b decode descramble serial to parallel max9276amax9280a revers e contro l channel hdcp decrypt (max9280aonly) hdcp decrypt control add[2:0] uart/i 2 c gpio_ gpi sd/him intout/add2 sc kw st x/ scl rx/ sda i2csel pwdn ms bws hdcp keys rgbhs vs de hs vs de acb cntl[3:0](9b10b) dout[28:27](30-bit) fcc hdcp control i 2 s/tdm add[2:0] fifo control (9b10b) data description registers sync video clkdiv sspll cdrpll cntl0, cntl3(9b10b) cntl[2:1 ] (9b10b) dout[28:27] (30-bit ) cntl0/add 0 cntl3/add 1 dout27/cntl1 dout28/cntl2 dout19 /v s dout18 /h s dout[26:21] dout[17:0 ] pclkout enable dout20/d e rgb[23:18] (30-bit or 9b10b) rgb[17:0] cml rx and eq cx/ tp in+ in- tx downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 21 figure 1. reverse control-channel output parameters figure 2. test circuit for differential input measurement max9276a max9280a reverse control-channel transmitter in+ in- in- in+ in+ in- v od r l /2 r l /2 v cmr v cmr v roh (in+) - (in-) t r 0.1 x v rol 0.9 x v rol t f v rol 0.9 x v roh 0.1 x v roh v in+ r l /2 r l /2 c in c in v id(p) in+ in- v id(p) = | v in+ - v in- | v cmr = (v in+ + v in- )/2 v in- _ + _ _ + downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 22 figure 4. worst-case pattern output figure 5. i 2 c timing parameters figure 6. parallel clock output requirements t note:

protocol scl sda start condition (s) bit 7 msb (a7) bit 6 (a6) bit 0 (r/w) acknowledge (a) stop condition (p) v iovdd x 0.7 v iovdd x 0.3 v iovdd x 0.7 v iovdd x 0.3 t su;sta t low t high t buf t hd;sta t r t sp t f t su;dat t hd;dat t vd;dat t vd;ack t su;sto 1/f scl ol max t high t low t t v oh min pclkout figure 3. test circuit for single-ended input measurement c in 0.22 f 49.9 ? + - v in_ in_ v is(p) downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 23 figure 7. output rise-and-fall times figure 8. deserializer delay figure 9. gpi-to-gpo delay 0.2 x v i0vdd t f t r c l single-ended output load !" bit in+/- dout_ pclkout last bit serial word n serial-word length serial word n+1 serial word n+2 t sd pa ralle l word n-2 pa ralle l word n- 1p aralle l word n note: pclkout programmed for rising l at ching edge. t gpio t gpio v oh_min v ol_max v ih_min v il_max deserializer gpi serializer gpo downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 24 detailed description the max9276a/max9280a deserializers, when paired with the max9275/max9277/max9279/max9281 serializers, provides the full set of operating features, but is backward-compatible with the max9249Cmax9270 family of gigabit multimedia serial link (gmsl) devices, and have basic functionality when paired with any gmsl device. the max9280a has high-bandwidth digital content protection (hdcp) while the max9276a does not. the deserializer has a maximum serial-bit rate of 3.12gbps for up to 15m of cable and operates up to a maximum output clock of 104mhz in 24-bit mode and 27-bit high- bandwidth mode, or 78mhz in 32-bit mode. this bit rate and output flexibility support a wide range of displays, from qvga (320 x 240) to 1920 x 720 and higher with 24-bit color, as well as megapixel image sensors. an encoded audio channel supports l-pcm i 2 s stereo and up to eight channels of l-pcm in tdm mode. sample rates of 32khz to 192khz are supported with sample depth from 8 to 32 bits. input equalization, combined with gmsl serializer pre/ deemphasis, extends the cable length and enhances link reliability the control channel enables a c to program the serializer and deserializer registers and program registers on peripherals. the control channel is also used to perform hdcp functions (max9280a only). the c can be located at either end of the link, or when using two cs, at both ends. two modes of control-channel operation are available. base mode uses either i 2 c or gmsl uart protocol, while bypass mode uses a user-defined uart protocol. uart protocol allows full-duplex communication, while i 2 c allows half-duplex communication. spread spectrum is available to reduce emi on the parallel output. the serial input complies with iso 10605 and iec 61000-4-2 esd protection standards. register mapping registers set the operating conditions of the deserializers and are programmed using the control channel in base mode. the max9276a/max9280a holds its own device address and the device address of the serializer it is paired with. similarly, the serializer holds its own device address and the address of the max9276a/max9280a. whenever a device address is changed be sure to write the new address to both devices. the default device address of the deserializer is set by the add[2:0] and cx/tp inputs (see table 1 ). registers 0x00 and 0x01 in both devices hold the device addresses. figure 10. lock time figure 11. power-up delay figure 12. output i 2 s timing parameters w# t d$ a t d$ % t d$ a t f t d$ % t r # s& # ' i() * i( * lock t lock pwdn must be high v oh +,- ./ lock t pu pwdn v oh v ih1 downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 25 output bit map the output bit width depends on settings of the bus width (bws) pin. table 2 lists the bit map. unused output bits are pulled low. serial link signaling and data format the serializer uses differential cml signaling to drive twisted-pair cable and single-ended cml to drive coaxial cable with programmable pre/deemphasis and ac-coupling. the deserializer uses ac-coupling and programmable channel equalization. input data is scrambled and then 8b/10b coded (9b/10b in high-bandwidth mode). the deserializer recovers the embedded serial clock, then samples, decodes, and descrambles the data. in 24-bit mode, the first 21 bits contain video data. in 32-bit mode, the first 29 bits contain video data. in high-bandwidth mode, the first 24 bits contain video data, or special control signal packets. the last 3 bits contain the embedded audio channel, the embedded forward control channel, the parity bit of the serial word ( figure 13 , figure 14 ). table 1. device address defaults (register 0x00, 0x01) *x = 0 for the serializer address, x = 1 for the deserializer address **cx/tp determine the serial cable type cx/tp = open addresses only for coax mode. pin device address (bin) serializer device address (hex) deserializer device address (hex) cx/tp** add2 add1 add0 d7 d6 d5 d4 d3 d2 d1 d0 high/low low low low 1 0 0 x* 0 0 0 r/ w 80 90 high/low low low high 1 0 0 x* 0 1 0 r/ w 84 94 high/low low high low 1 0 0 x* 1 0 0 r/ w 88 98 high/low low high high 0 1 0 x* 0 1 0 r/ w 44 54 high/low high low low 1 1 0 x* 0 0 0 r/ w c0 d0 high/low high low high 1 1 0 x* 0 1 0 r/ w c4 d4 high/low high high low 1 1 0 x* 1 0 0 r/ w c8 d8 high/low high high high 0 1 0 x* 1 0 0 r/ w 48 58 open low low low 1 0 0 x* 0 0 x* r/ w 80 92 open low low high 1 0 0 x* 0 1 x* r/ w 84 96 open low high low 1 0 0 x* 1 0 x* r/ w 88 9a open low high high 0 1 0 x* 0 1 x* r/ w 44 56 open high low low 1 1 0 x* 0 0 x* r/ w c0 d2 open high low high 1 1 0 x* 0 1 x* r/ w c4 d6 open high high low 1 1 0 x* 1 0 x* r/ w c8 da open high high high 0 1 0 x* 1 0 x* r/ w 48 5a downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 26 table 2. output map *see the high-bandwidth mode section for details on timing requirements. +outputs used only when the respective color lookup tables are enabled. **not encrypted when hdcp is enabled (max9280a only). figure 13. 24-bit mode serial-data format signal output pin mode 24-bit mode (bws = low) high-bandwidth mode (bws = mid 32-bit mode (bws = high) r[5:0] dout[5:0] used used used g[5:0] dout [11:6] used used used b[5:0] dout [17:12] used used used hs, vs, de dout18/hs, dout19/vs, dout20/de used** used** used** r[7:6] dout [22:21] used+ used used g[7:6] dout [24:23] used+ used used b[7:6] dout [26:25] used+ used used cntl[2:1] dout [28:27]/cntl[2:1] not used used*/** used** cntl3, cntl0 cntl3/add1, cntl0/add0 not used used*/** not used i 2 s/tdm ws, sck, sd/him used used used aux signal used used used d0 serial da ta output pin output signal d1 dout 0 r0 r1 b5 hs vs de dout 1 d17 d18 24 bits d19 d20 acb audio decode for wa rd control- channel bit pa cket pa rity- check bi t fcc pcb dout 17 dout 18/hs dout 19/vs dout 20/de ws sck sd rx/ sda tx/ scl rgb data control bits i 2 s/ tdm audio uart /i 2 c max9280a note : vs /h s must be set at dout[19:18] for hdcp functionality.only dout[17:0] and acb have hdcp decryption. downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 27 figure 14. 32-bit mode serial-data format figure 15. high-bandwidth mode seria-data format d0 serial da ta output pin output signal d1 dout 0 r0 r1 b5 dout 1 d17 d18 dout 17 dout 18/hs d19 d20 dout 19/vs dout 20/de d21 d22 dout 21 dout 22 d23 32 bits d24 dout 23 dout 24 d25 d26 dout 25 dout 26 d27 d28 dout27/ cntl1 dout28/ cntl2 ws acb fcc sck pcb sd rx/ sda tx/ scl audio decode for wa rd control- channel bit pa cket pa rity- check bi t hs vs de r6 r7 g6 g7 b6 b7 rgb data control bits rgb data max9280a note: v s/h s must be set at dout[19:18] for hdcp functionality. only dout[17:0], dout[26:21] and acb have hdcp encryption. i 2 s/ tdm audio uart /i 2 c aux control bits d0 serial da ta d1 27 bits input pin dout 0 dout 1 d17 d18 d19 d20 d21 d22 d23 acb fcc pcb dout 17 dout 21 dout 22 dout 23 dout 24 dout 25 dout 26 ws sck sd rx/ sda tx/ scl input signal r0 r1 b5 r6 r7 g6 g7 b6 b7 hs vs de rgb data rgb data i 2 s/ tdm audio uart /i 2 c max9280a note: vs /h s must be set at dout[20:18] . only dout[17:0], dout[26:21] and acb have hdcp encryption . audio decode for wa rd control- channel bit pa cket pa rity- check bit special serial-da ta pa cket cntl0/ add0 dout27/ cntl1 dout28/ cntl2 cntl3 add1 dout 18/hs dout 19/vs dout 20/de aux control bits control bits control signal decoding 27 bits downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 28 the deserializer uses the drs bit and the bws input to set the pclkout frequency range ( table 3 ). set drs = 1 for low data rate pclkout frequency range of 6.25mhz to 16.66mhz. set drs = 0 for high data rate pclkout frequency range of 12.5mhz to 104mhz. high-bandwidth mode the deserializer uses a 27-bit high-bandwidth mode to support 24-bit rgb at 104mhz pixel clock. set bws = open in both the serializer and deserializer to use high- bandwidth mode. in high-bandwidth mode, the deserial - izer decodes hs, vs, de and cntl[3:0] from special packets. packets are sent by replacing a pixel before the rising edge and after the falling edge of the hs, vs, and de signals. however, for cntl[3:0], which is not always continuously sampled, packets always replace a pixel before the transition of the sampled cntl[3:0]. keep hs, vs, and de low pulse widths at least 2 pixel clock cycles. by default, cntl[3:0] are sampled continuously when de is low. cntl[3:0] are sampled only on hs/vs transitions when de is high. if de triggering of encoded packets is not desired, set the serializers disdetrig = 0 and the cntltrig bits to their desired value (register 0x15) to change the cntl triggering behavior. set detren = 0 on the deserializer when de is not periodic. audio channel the audio channel supports 8khz to 192khz audio sampling rates and audio word lengths from 8 bits to 32 bits (2 channel i 2 s) or 64 to 256 bits (tdm64 to tdm256). the audio bit clock (sck) does not have to be synchronized with pclkout. the serializer automatically encodes audio data into a single-bit stream synchronous with pclkout. the deserializer decodes the audio stream and stores audio words in a fifo. audio rate detection uses an internal oscillator to continuously determine the audio data rate and output the audio in i 2 s format. the audio channel is enabled by default. when the audio channel is disabled, the sd/him is treated as an auxiliary control signal. since the audio data sent through the serial link is syn- chronized with pclkout, low pclkout frequencies limit the maximum audio sampling rate. table 4 lists the maximum audio sampling rate for various pclkout fre- quencies. spread-spectrum settings do not affect the i 2 s/ tdm data rate or ws clock frequency. audio channel input the audio channel input works with 8-channel tdm and stereo i 2 s, as well as non-standard formats. the input format is shown in figure 16 . table 3. data-rate selection table figure 16. audio channel input format drs bit setting bws pin setting pclkout range (mhz) 0 (high data rate) low (24-bit mode) 16.66 to 104 mid (high-bandwidth mode) 36.66 to 104 high (32-bit mode) 12.5 to 78 1 (low data rate) low 8.33 to 16.66 mid 18.33 to 36.66 high 6.25 to 12.5 fram e 16 to 256 bits 012 sck sd ws n downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 29 table 4. maximum audio ws frequency (khz) for various pclkout frequencies +max ws rate is greater than 192khz. *drs = 0 pclkout frequency is equal to 2x the drs = 1 pclkout frequency. channels bits per channel pclkout frequency (drs = 0*) (mhz) 12.5 15.0 16.6 20.0 25.0 30.0 35.0 40.0 45.0 50.0 100 2 8 + + + + + + + + + + + 16 + + + + + + + + + + + 18 185.5 + + + + + + + + + + 20 174.6 + + + + + + + + + + 24 152.2 182.7 + + + + + + + + + 32 123.7 148.4 164.3 + + + + + + + + 4 8 + + + + + + + + + + + 16 123.7 148.4 164.3 + + + + + + + + 18 112.0 134.4 148.8 179.2 + + + + + + + 20 104.2 125.0 138.3 166.7 + + + + + + + 24 88.6 106.3 117.7 141.8 177.2 + + + + + + 32 69.9 83.8 92.8 111.8 139.7 167.6 + + + + + 6 8 152.2 182.7 + + + + + + + + + 16 88.6 106.3 117.7 141.8 177.2 + + + + + + 18 80.2 93.3 106.6 128.4 160.5 + + + + + + 20 73.3 88.0 97.3 117.3 146.6 175.9 + + + + + 24 62.5 75.0 83.0 100 125 150 175 + + + + 32 48.3 57.9 64.1 77.2 96.5 115.9 135.2 154.5 173.8 + + 8 8 123.7 148.4 164.3 + + + + + + + + 16 69.9 83.8 92.8 111.8 139.7 167.6 + + + + + 18 62.5 75.0 83.0 100.0 125.0 150.0 175.0 + + + + 20 57.1 68.5 75.8 91.3 114.2 137.0 159.9 182.7 + + + 24 48.3 57.9 64.1 77.2 96.5 115.9 135.2 154.5 173.8 + + 32 37.1 44.5 49.3 59.4 74.2 89.1 103.9 118.8 133.6 148.4 + color coding < 48khz48khz to 96khz 96khz to 192khz > 192khz downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 30 the period of the ws can be 8 to 256 sck periods. the ws frame starts with the falling edge and can be low for 1 to 255 sck periods. sd is one sck period, sampled on the rising edge. msb/lsb order, zero padding or any other significance assigned to the serial data does not affect operation of the audio channel. the polarity for ws and sck edges is programmable. figure 17 , figure 18 , figure 19 , and figure 20 are examples of acceptable input formats. figure 17. 8-channel tdm (24-bit samples, padded with zeros) figure 18. 6-channel tdm (24-bit samples, no padding) figure 19. stereo i 2 s (24-bit samples, padded with zeros) ws sck sd ch1 32 sck ch2 ch3 ch4 ch5 256 sck ch6 ch7 ch8 msb 24-bit data lsb 8 bits zero 0 1 1 2 3 sd c 45 c 46 c 47 c 48 c 49 c 4: 68 ;c< 68 =>?@ be@ e 588 ;c < 32 sck 64 sck left channe l right channe l ws sck sd msb 24-bit data lsb 8 bits zero downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 31 audio channel output ws, sck, and sd are output with the same timing rela- tionship they had at the audio input, except that ws is always 50% duty cycle (regardless of the duty cycle of ws at the input). the output format is shown in figure 21 . ws and sck can be driven by the audio source (clock master) or the audio sink (clock slave). buffer underflow and overflow flags are available to the sink as clock slave via i 2 c for clock frequency adjustment. data are sampled on the rising edge. ws and sck polarity is programmable. figure 20. stereo i 2 s (16-bit samples, no padding) figure 21. audio channel output format gh jk l mnop k qtuun m v ight channe l 16 sck 16-bit data ws sck sd i 2 s tdm 256 sck sd/him ws sck sd/him ws 8 to 32 bits 256 bits downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 32 additional mclk output for audio applications some audio dacs, such as the max9850, do not require a synchronous main clock (mclk), while other dacs require a separate mclk for operation. for audio applications that cannot use ws or pclkout directly, the deserializer provides a divided mclk output at either dout28/cntl2 or cntl0/add0 (determined by mclkpin bit setting) at the expense of one less control line. by default, mclk is turned off. set mclkdiv (deserializer register 0x12, d[6:0]) to a nonzero value to enable the mclk output. set mclkdiv to 0x00 to disable mclk and set dout28/cntl2 or cntl0/add0 as a control output. the output mclk frequency is: src mclk f f mclkdiv = where:f src is the mclk source frequency (see table 5 ) mclkdiv is the divider ratio from 1 to 127 choose mclkdiv values so that f mclk is not greater than 60mhz. mclk frequencies derived from pclkout (mclksrc = 0) are not affected by spread-spectrum settings in the deserializer. enabling spread spectrum in the serializer, however, introduces spread spectrum into mclk. spread-spectrum settings of either device do not affect mclk frequencies derived from the internal oscillator. the internal oscillator frequency ranges from 100mhz to 150mhz over all process corners and operating conditions. alternatively, set mclkws = 1 (0x15 d1) to output ws from mclk. audio output timing sources the deserializer has multiple options for audio data output timing. by default, the deserializer provides the output timing based on the incoming data rate (through a fifo) and an internal oscillator. to use a system sourced clock, set the audiomode bit to 1 (d5 of register 0x02) to set ws and sck as inputs on the deserializer side. the deserializer uses a fifo to smooth out the differences in input and output audio timing. registers 0x78 and 0x79 store the fifo overflow/ underflow information for use with external ws/sck timing. the fifo drops data packets during fifo over- flow. by default, the fifo repeats the last audio packet during fifo underflow when no audio data is available. set the audufbeh bit (d2 of register 0x01d) to 1 to output all zeroes during underflow. reverse control channel the serializer uses the reverse control channel to receive i 2 c/uart and gpo signals from the deserializer in the opposite direction of the video stream. the reverse control channel and forward video data coexist on the same serial cable forming a bidirectional link. the reverse control channel operates independently from the forward control channel. the reverse control channel is available 2ms after power-up. the serializer temporarily disables the reverse control channel for 500s after starting/ stopping the forward serial link. table 5. f src settings *mclk is not divided when using ws as the mclk source. the mclk divider must still be set to a nonzero number for mclk to be enabled. mclkws setting (register 0x15, d1) mclksrc setting (register 0x12, d7) data rate setting bit-width setting mclk source frequency (f src ) 0 0 high speed (drs = 0) 24-bit or high-bandwidth mode 3 x f clkout 32-bit mode 4 x f clkout low speed (drs = 1) 24-bit or high-bandwidth mode 6 x f clkout 32-bit mode 8 x f clkout 1 internal oscillator (120mhz typ) 1 ws* downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 33 control channel and register programming the control channel is available for the c to send and receive control data over the serial link simultaneously with the high-speed data. the c controls the link from either the serializer or the deserializer side to support video-display or image-sensing applications. the control channel between the c and serializer or deserializer runs in base mode or bypass mode according to the mode selection (ms) input of the device connected to the c. base mode is a half-duplex control channel and the bypass mode is a full-duplex control channel. the total maximum forward or reverse control-channel delay is 2s (uart) or 2-bit times (i 2 c) from the input of one device to the output of the other. i 2 c delay is measured from a start condition to start condition. uart interface in base mode, the c is the host and can access the registers of both the serializer and deserializer from either side of the link using the gmsl uart protocol. the c can also program the peripherals on the remote side by sending the uart packets to the serializer or deserializer, with the uart packets converted to i 2 c by the device on the remote side of the link. the c communicates with a uart peripheral in base mode (through inttype register settings), using the half-duplex default gmsl uart protocol of the serializer/deserializer. the device addresses of the serializer and deserializer in base mode are programmable. when the peripheral interface is i 2 c, the serializer/ deserializer converts uart packets to i 2 c that have device addresses different from those of the serializer or deserializer. the converted i 2 c bit rate is the same as the original uart bit rate. the deserializer uses differential line coding to send signals over the reverse channel to the serializer. the bit rate of the control channel is 9.6kbps to 1mbps in both directions. the serializer and deserializer automatically detect the control-channel bit rate in base mode. packet bit rate changes can be made in steps of up to 3.5 times higher or lower than the previous bit rate. see the changing the clock frequency section for more information. figure 22 shows the uart protocol for writing and reading in base mode between the c and the serializer/ deserializer. figure 23 shows the uart data format. even parity is used figure 24 and figure 25 detail the formats of the sync byte (0x79) and the ack byte (0xc3). the c and the connected slave chip generate the sync byte and ack byte, respectively. events such as device wake-up and gpi generate transitions on the control channel that can be ignored by the c. data written to the deserializer registers do not take effect until after the acknowledge byte is sent. this allows the c to verify that write commands are received without error, even if the result of the write command directly affects the serial link. the slave uses the sync byte to synchronize with the host uarts data rate. if the gpi or ms inputs of the deserializer toggle while there is control-channel communication, or if a line fault occurs, the control-channel communication will be corrupted. in the event of a missed or delayed acknowledge (~1ms due to control-channel timeout), the c should assume there was an error in the packet transmission or response. in base mode, the c must keep the uart tx/rx lines high no more than 4 bit-times between bytes in a packet. keep the uart tx/rx lines high for at least 16 bit-times before starting to send a new packet. figure 22. gmsl uart protocol for base mode xy z[\ ]^ [^ form at sync dev addr + r/w reg addr number of bytes sync dev addr + r/w reg addr number of bytes byte 1 byte n ack byte n byte 1 ack master reads from slave read da ta form at master writes to sl av e master writes to sl av e master reads from slave downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 34 as shown in figure 26 , the remote-side device converts packets going to or coming from the peripherals from uart format to i 2 c format and vice versa. the remote device removes the byte number count and adds or receives the ack between the data bytes of i 2 c. the i 2 c bit rate is the same as the uart bit rate. figure 23. gmsl uart data format for base mode figure 26. format conversion between gmsl uart and i 2 c with register address (i2cmethod = 0) figure 24. sync byte (0x79) figure 25. ack byte (0xc3) start base mode uses even parity. d0 d1 d2 d3 d4 d5 d6 d7 parity stop 1 uart frame frame 1 frame 2 frame 3 stop start stop start _ `ab ` c d e d d e e e e d c e c f d3 c g c h c i c j k abl`m stop nopq o rs t t s s s s t t r t ru rv rw rx ry rz {p q|o} stop ~~ ??? ??? ?? register address number of bytes device id + wr da ta 0 dev id a 11 11 11 11 da ta n 11 11 s 1 1 1 ack frame 7 : master to sl av e 8 serializer/deserializer peripheral w 1 reg addr 8 a 11 81 11 sync frame register address number of bytes device id + rd 11 11 11 11 ack frame da ta 0 11 da ta n 11 uar t- to -i 2 c conversion of write packet (i2cmethod = 0) uar t- to -i 2 c conversion of read packet (i2cmethod = 0) s: start p: stop a: acknowledge : slave to master da ta 0a da ta na p dev id a s 11 7 w 1 dev id a s 11 7 r 1 da ta np 1 8 a 1 da ta 0 8 a 1 reg addr 8 a 1 c serializer/deserializer c serializer/deserializer serialize r/ deserializer peripheral downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 35 interfacing command-byte-only i 2 c devices with uart the deserializers uart-to-i 2 c conversion can interface with devices that do not require register addresses, such as the max7324 gpio expander. in this mode, the i 2 c master ignores the register address byte and directly reads/ writes the subsequent data bytes ( figure 27 ). change the communication method of the i 2 c master using the i2cmethod bit. i2cmethod = 1 sets command-byte- only mode, while i2cmethod = 0 sets normal mode where the first byte in the data stream is the register address. uart bypass mode in bypass mode, the deserializers ignore uart commands from the c and the c communicates with the peripherals directly using its own defined uart protocol. the c cannot access the serializer/ deserializers registers in this mode. peripherals accessed through the forward control channel using the uart interface need to handle at least one pclkout period 10ns of jitter due to the asynchronous sampling of the uart signal by pclkout. set ms/hven = high to put the control channel into bypass mode. for applications with the c connected to the deserializer, there is a 1ms wait time between setting ms high and the bypass control channel being active. there is no delay time when switch - ing to bypass mode when the c is connected to the serializer. do not send a logic-low value longer than 100s to ensure proper gpo functionality. bypass mode accepts bit rates down to 10kbps in either direction. see the gpo/gpi control section for gpi functionality limitations. the control-channel data pattern should not be held low longer than 100s if gpi control is used. figure 27. format conversion between gmsl uart and i 2 c with register address (i2cmethod = 1) ? ?? ???? to sl av e serializer/deserializer serializer/deserializer serializer/deserializer uar t- to -i 2 c conversion of read packet (i2cmethod = 1) uar t- to -i 2 c conversion of write packet (i2cmethod = 1) c serializer/deserializer c sync frame 11 11 11 11 11 11 11 11 11 11 11 11 11 11 device id + rd register address number of bytes sync frame device id + wr register address number of bytes da ta 0d at a n ack frame ack frame da ta 0d at a n da ta n a da ta 0 wa dev id s ap peripheral peripheral s 11 18 88 1 11 17 11 8 11 1 7 dev id ra aa p da ta 0d at a n : slave to master s: start p: stop a: acknowledge downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 36 i 2 c interface in i 2 c to i 2 c mode, the deserializers control-channel interface sends and receives data through an i 2 c-compatible 2-wire interface. the interface uses a serial-data line (sda) and a serial-clock line (scl) to achieve bidirectional communication between master and slave(s). a c master initiates all data transfers to and from the device and generates the scl clock that synchronizes the data transfer. when an i 2 c transaction starts on the local-side devices control-channel port, the remote-side devices control-channel port becomes an i 2 c master that interfaces with remote-side i 2 c peripherals. the i 2 c master must accept clock-stretching which is imposed by the deserializer (holding scl low) the sda and scl lines operate as both an input and an open- drain output. pullup resistors are required on sda and scl. each transmission consists of a start condition ( figure 5 ) sent by a master, followed by the devices 7-bit slave address plus a r/w bit, a register address byte, one or more data bytes, and finally a stop condition. start and stop conditions both scl and sda remain high when the interface is not busy. a master signals the beginning of a transmission with a start (s) condition by transitioning sda from high to low while scl is high (see figure 28 ). when the master has finished communicating with the slave, it issues a stop (p) condition by transitioning sda from low to high while scl is high. the bus is then free for another transmission. bit transfer one data bit is transferred during each clock pulse ( figure 29 ). the data on sda must remain stable while scl is high. figure 28. start and stop conditions figure 29. bit transfer ??? ?? ? ?? ? ? ? condition stop condition s p ?? ? ? ?? ? ? ?? ? ??? ?? ?? ? ? ? ? ? ?? ?? ? ?? change of da ta allowed downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 37 acknowledge the acknowledge bit is a clocked 9th bit that the recipient uses to handshake receipt of each byte of data ( figure 30 ). thus, each byte transferred effectively requires nine bits. the master generates the 9th clock pulse, and the recipient pulls down sda during the acknowledge clock pulse. the sda line is stable low during the high period of the clock pulse. when the master is transmitting to the slave device, the slave device generates the acknowl - edge bit because the slave device is the recipient. when the slave device is transmitting to the master, the master generates the acknowledge bit because the master is the recipient. the device generates an acknowledge even when the forward control channel is not active. to prevent acknowledge generation when the forward control channel is not active, set the i2clocack bit low. slave address the deserializers have 7-bit long slave addresses. the bit following a 7-bit slave address is the r/w bit, which is low for a write command and high for a read command. the slave address for the deserializer is xx01xxx1 for read commands and xx01xxx0 for write commands. see figure 31 . bus reset the device resets the bus with the i 2 c start condition for reads. when the r/w bit is set to 1, the deserializers transmit data to the master, thus the master is reading from the device. figure 30. acknowledge figure 31. slave address | by ? |? a?? clock pulse for acknowledge star t condition sda by receiver 1 2 8 9 s -? x - 2 3 - 2- x x ? ? 1 xx downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 38 format for writing writes to the deserializers comprise the transmission of the slave address with the r/w bit set to zero, followed by at least one byte of information. the first byte of infor - mation is the register address or command byte. the register address determines which register of the device is to be written by the next byte, if received. if a stop (p) condition is detected after the register address is received, the device takes no further action beyond storing the register address ( figure 32 ). any bytes received after the register address are data bytes. the first data byte goes into the register selected by the register address, and subsequent data bytes go into subsequent registers ( figure 33 ). if multiple data bytes are transmitted before a stop condition, these bytes are stored in subsequent registers because the register addresses autoincrements. figure 32. format for i 2 c write figure 33. format for write to multiple registers o ? ? ? ? ??? ? o o ? a? ? ? ? ? ?? 0 0 0 0 ? 0 0 0 0 register address = 0x00 0 0 0 0 a p d7 d6 d5 d4 register 0x00 write da ta d3 d2 d1 d0 a s = star t bit p = stop bit a = ack d_ = da ta bi t ? ? ? ? ? op bit a = ack n = nackd_ = da ta bi t s 1 0 0 0 address = 0x80 0 = write 0 0 0 0 a 0 0 0 0 register address = 0x00 0 0 0 0 a d7 d6 d5 d4 register 0x00 write da ta d3 d2 d1 d0 ad 7 p d6 d5 d4 register 0x01 write da ta d3 d2 d1 d0 n downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 39 format for reading the deserializers are read using the internally stored register address as an address pointer, the same way the stored register address is used as an address pointer for a write. the pointer autoincrements after each data byte is read using the same rules as for a write. thus, a read is initiated by first configuring the register address by performing a write ( figure 34 ). the master can now read consecutive bytes from the device, with the first data byte being read from the register address pointed by the previously written register address. once the master sends a nack, the device stops sending valid data. i 2 c communication with remote-side devices the deserializers support i 2 c communication with a peripheral on the remote side of the communication link using scl clock stretching. while multiple masters can reside on either side of the communication link, arbitration is not provided. the connected masters need to support scl clock stretching. the remote-side i 2 c bit-rate range must be set according to the local-side i 2 c bit rate. supported remote-side bit rates can be found in table 6 . set the i2cmstbt (register 0x1c) to set the remote i 2 c bit rate. if using a bit rate different from 400kbps, local and remote-side i 2 c setup and hold times should be adjusted by setting the i2cslvsh register settings on both sides. i 2 c address translation the deserializers support i 2 c address translation for up to two device addresses. use address translation to assign unique device addresses to peripherals with limited i 2 c addresses. source addresses (address to translate from) are stored in registers 0x18 and 0x1a. destination addresses (address to translate to) are stored in registers 0x19 and 0x1b. in a multilink situation where there are multiple deserializers and/or peripheral devices connected to these serializers, the deserializers support broadcast commands to control these multiple devices. select an unused device address to use as a broadcast device address. program all the remote-side serializer devices to translate the broadcast device address (source address stored in registers 0x0f, 0x11) to the peripherals address (destination address stored in registers 0x10, 0x12). any commands sent to the broadcast address (selected unused address) will be sent to all deserializers and/or peripheral devices connected to the deserializers whose addresses match the translated broadcast address. figure 34. format for i 2 c read table 6. i 2 c bit-rate ranges local bit rate remote bit-rate range i2cmstbt setting f > 50kbps up to 1mbps any 20kbps > f > 50kbps up to 400kbps up to 110 f < 20kbps up to 10kbps 000 s = star t bit p = stop bit a = ack n = nackd_ = da ta bi t s s 1 0 0 0 address = 0x80 0 = write 0 0 0 0 a 1 = read repeated start 0 0 0 0 register address = 0x00 0 0 0 0 a 1 0 0 0 address = 0x81 0 0 0 1 ad 7 p d6 d5 d4 register 0x00 read da ta d3 d2 d1 d0 n downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 40 gpo/gpi control gpo on the serializer follows gpi transitions on the deserializer. this gpo/gpi function can be used to transmit signals such as a frame sync in a surround-view camera system. the gpi to gpo delay is 0.35ms max. keep time between gpi transitions to a minimum 0.35ms. this includes transitions from the other deserializer in coax splitter mode. bit d4 of register 0x06 in the deserializer stores the gpi input state. gpo is low after power-up. the c can set gpo by writing to the setgpo register bit. do not send a logic-low value on the deserializer rx/ sda input (uart mode) longer than 100s in either base or bypass mode to ensure proper gpo/gpi functionality. line equalizer the deserializer includes an adjustable line equalizer to further compensate cable attenuation at high frequencies. the cable equalizer has 11 selectable levels of compensation from 2.1db to 13db ( table 7 ). to select other equalization levels, set the corresponding register bits in the deserializer (0x05 d[3:0]). use equalization in the deserializer, together with preemphasis in the serializer, to create the most reliable link for a given cable. spread spectrum to reduce the emi generated by the transitions on the serial link, the deserializer output is programmable for spread spectrum. if the serializer, paired with the max9276a/max9280a, has programmable spread spectrum, do not enable spread for both at the same time or their interaction will cancel benefits. the deserializer will track the serializer spread and pass the spread to the deserializer output. the programmable spread-spectrum amplitudes are 2%,and 4% ( table 8 ). the deserializer includes a sawtooth divider to control the spread modulation rate. autodetection of the pclkout operation range guarantees a spread-spectrum modulation frequency within 20khz to 40khz. additionally, manual configuration of the sawtooth divider (sdiv: 0x03, d[5:0]) allows the user to set a modulation frequency according to the pclkout frequency. when ranges are manually selected, program the sdiv value for a fixed modulation frequency around 20khz. manual programming of the spread-spectrum divider the modulation rate relates to the pclkout frequency as follows: ( ) pclkout m f f 1 drs mod sdiv = + where:f m = modulation frequency drs = drs value (0 or 1) f pclkout = pclkout frequency mod = modulation coefficient given in table 9 sdiv = 5-bit sdiv setting, manually programmed by the c to program the sdiv setting, first look up the modulation coefficient according to the desired bus-width and spread- spectrum settings. solve the above equation for sdiv using the desired pixel clock and modulation frequencies. if the calculated sdiv value is larger than the maximum allowed sdiv value in table 9 , set sdiv to the maximum value. table 7. cable equalizer boost levels table 8. output spread table 9. modulation coefficients and maximum sdiv settings boost setting (0x05 d[3:0]) typical boost gain (db) 0000 2.1 0001 2.8 0010 3.4 0011 4.2 0100 5.2 0101 6.2 0110 7 0111 8.2 1000 9.4 1001 10.7 power-up default 1010 11.7 1011 13 ss spread (%) 00 no spread spectrum. power-up default. 01 2% spread spectrum. 10 no spread spectrum 11 4% spread spectrum spread- spectrum setting (%) modulation coefficient mod (decimal) sdiv upper limit (decimal) 4 208 15 2 208 30 downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 41 hs/vs/de tracking the deserializer has tracking to filter out hs/vs/de bit or packet errors. hs/vs/de tracking is on by default when the device is in high-bandwidth mode (bws = open), and off by default when in 24-bit or 32-bit mode (bws = low or high). set/clear hvtren (d6 of register 0x15) to enable/disable hs/vs tracking. set/clear detren (d5 of register 0x15) to enable/disable de tracking. by default, the device uses a partial and full periodic tracking of hs/de. set hvtrmode = 0 (d4 of register 0x15) to disable full periodic tracking. hs/vs/de tracking can be turned on in 24-bit and 32-bit modes to track and correct against bit errors in hs/vs/de link bits. serial input the device can receive serial data from two kinds of cable: 100 twisted pair and 50 coax. (contact the fac- tory for devices compatible with 75 cables). coax splitter mode in coax mode, out+ and out- of the serializer are active. this enables the use as a 1:2 splitter ( figure 35 ). in coax mode, connect out+ to in+ of the deserializer. connect out- to in- of the second deserializer. control-channel data is broadcast from the serializer to both deserializers and their attached peripherals. assign a unique address to send control data to one deserializer. leave all unused in_ pins unconnected, or connect them to ground through 50 and a capacitor for increased power-supply rejection. if out- is not used, connect out- to v dd through a 50 resistor ( figure 36 ). when there are cs at the serializer, and at each deserializer, only one c can communicate at a time. disable forward and reverse channel links according to the communicating deserializer connection to prevent contention in i 2 c to i 2 c mode. use enrevp or enrevn register bits to disable/enable the control- channel link. in uart mode, the serializer provides arbitration of the control-channel link. cable-type coniguration input cx/tp determine the power-up state of the serial input. in coax mode, cx/tp also determine which coax input is active, along with the default device address ( table 10 ). figure 35. 2:1 coax splitter connection diagram figure 36. coax connection diagram table 10. configuration input map cx/tp function high coax+ input. 7-bit device address is xxxxxx0 (bin). mid coax- input. 7-bit device address is xxxxxx1 (bin). low twisted-pair input. 7-bit device address is xxxxxx0 (bin). out+ out- optional components for increased power-supply rejection in+in- in+in- max9276amax9280a max9276a max9280a gmsl serializer out+ out- in+ optional components for increased power-supply rejection in- avdd 50 max9276amax9280a gmsl serializer downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 42 color lookup tables the deserializer includes three color lookup tables (lut) to support automatic translation of rgb pixel values. this feature can be used for color gamma correction, brightness/contrast or for other purposes. there are three lookup tables, each 8 bits wide and 256 entries deep, enabling a 1-to-1 translation of 8-bit input values to any 8-bit output value for each color (24 bits total). programming and verifying lut data the c must set the lutprog register bit to 1 before programming and verifying the tables. to program a lut, the c generates a write packet with register address set to the assigned register address for respective lut (0x7d, 0x7e, or 0x7f). the deserializer writes data in the packet to the respective lut starting from the lut address location set in lutaddr register. successive bytes in the data packet are written to the next lut address location, however each new data packet write starts from the address location stored in the lutaddr register. use 0x00 for lutaddr and 0x00 as the number of bytes field in uart packet, when writing a 256 byte data-block, because 8-bit wide number of bytes field cannot normally represent 9-bit wide 256 value. there is no number of bytes field in i 2 c-to-i 2 c modes. to read back the contents of an lut, the c generates a read packet with register address set to the assigned register address for respective lut (0x7d, 0x7e, or 0x7f). the deserializer outputs read data from the respective lut starting from the lut address location set in the lut_addr register. similar to the write operation, use 0x00 for lutaddr and 0x00 as the number of bytes field in uart packet, when reading a 256-byte data block. lut color translation after power-up or going out of sleep or power-down modes, lut translation is disabled and lut contents are unknown. after program and verify operations are finished, in order to enable lut translations, set lutprog bit to 0 and set the respective lut enable bits (red_lut_en, grn_lut_en, blu_lut_en) to 1 to enable the desired lut translation function. only the selected colors are translated by the lut (the other colors are not touched). the c does not need to fill in all three color lookup tables if all 3 color translations are not needed. after a pixel is deserialized decoded and decrypted (if necessary) it is segmented into its color components red, green and blue according to table 11 and figure 37 . if lut translation is enabled, each 8-bit pre-translation color value is used as address to the respective lut table to look up the corresponding (translated) 8-bit color value. lut bit width in 32-bit mode and high-bandwidth mode, 24 bits are available for color data (8 bits per color) and each lut is used for 8-bit to 8-bit color translation. in 24-bit mode, the deserializer can receive only up to 18-bit color (6 bits per color). the lut tables can translate from 6-bit to 6-bit, using the first 64 locations (0x00 to 0x3f). program the msb 2 bits of each lut value to 00. alternatively, program full 8-bit values to each lut for 6-bit to 8-bit color translation. table 11. pixel data format dout [5:0] dout [11:6] dout [17:12] dout 18 dout 19 dout 20 dout [22:21] dout [24:23] dout [26:25] r[5:0] g[5:0] b[5:0] hs vs de r[7:6] g[7:6] b[7:6] downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 43 figure 37. lut dataflow recommended lut program procedure 1) write lutprog = 1 to register 0x7c. keep bluluten = 0, grnluten = 0, redluten = 0 (write 0x08 to register 0x7c). 2) write contents of red lut with a single write packet. for 24-bit rgb, use 0x7d as register address and 0x00 as number of bytes (uart only) and write 256 bytes. for 18-bit rgb, use 0x7d as register address and 0x40 as number of bytes (uart only) and write 64 bytes. (optional: multiple write packets can be used if lutaddr is set before each lut write packet.) 3) read contents of red lut and verify that they are correct. use the same register address and number of bytes used in the previous step. 4) repeat steps 2 and 3 for the green lut, using 0x7e as the register address 5) repeat steps 2 and 3 for the blue lut, using 0x7f as the register address 6a) to finish the program and verify routine, without enabling the lut color translation, write lutprog = 0 (write 0x00 to register 0x7c). 6b) to finish the program and verify routine, and start lut color translation, write lutprog = 0, bluluten = 1, grnluten = 1, redluten = 1 (write 0x07 to register 0x7c). addr r5 r4 r3 r2 r1 r0 24-bit mode 32-bit or high- bandwidth mode r7 r6 00 red lut da ta msb lsb msb lsb dout 3 dout 9 dout 8 dout 7 dout 6 dout 2 dout 1 dout 0 dout 4 dout 5 r5 r4 r3 r2 r1 r0 r6 r7 addr g5 g4 g3 g2 g1 g0 g7 g6 00 green lut da ta msb lsb msb lsb g5 g4 g3 g2 g1 g0 g6 g7 addr b5 b4 b3 b2 b1 b0 b7 b6 00 blue lut da ta msb lsb msb lsb b5 b4 b3 b2 b1 b0 b6 b7 en redluten en grnluten en bluluten dout 22 dout 24 dout 26 dout 25 dout 17 dout 16 dout 15 dout 14 dout 13 dout 12 dout 23 dout 11 dout 10 dout 21 output pin output signal 24-bit mode 32-bit or high- bandwidth mode 24-bit mode 32-bit or high- bandwidth mode downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 44 high-immunity reverse control-channel mode the deserializer contains a high-immunity reverse control- channel mode, which has increased robustness at half the bit rate over the standard gmsl reverse control-channel link ( table 12 ). connect a 30k resistor to gpo/him on the serializer, and sd/him on the deserializer to use high- immunity mode at power-up. set the highimm bit high in both the serializer and deserializer to enable high-immunity mode at any time after power-up. set the highimm bit low in both the serializer and deserializer to use the legacy reverse control-channel mode. the deserializer reverse channel mode is not available for 500s/1.92ms after the reverse control-channel mode is changed through the serializer/deserializers highimm bit setting, respectively. the user must set sd/him and gpo/him or the highimm bits to the same value for proper reverse control-channel communication. in high-immunity mode, set hpftune = 00 in the equalizer, if the serial bit rate = [pclkout x 30 (bws = low or open) or 40 (bws = high)] is larger than 1gbps when bws is low or high. when bws = open, set hpftune = 00 when the serial bit rate is larger than 2gbps. in addition, use 47nf ac-coupling capacitors. note that legacy reverse control-channel mode may not function when using 47nf ac-coupling capacitors. by default, high-immunity mode uses a 500kbps bit rate. set revfast =1 (d7 in register 0x1a in the serializer and register 0x11 in the deserializer) in both devices to use a 1mbps bit rate. certain limitations apply when using the fast high-immunity mode ( table 13 ). sleep mode the deserializers have sleep mode to reduce power consumption. the devices enter or exit sleep mode by a command from a remote c using the control channel. set the sleep bit to 1 to initiate sleep mode. entering sleep mode resets the hdcp registers, but not the configuration registers. the deserializer sleeps after serial link inactivity or 8ms (whichever arrives first) after setting its sleep = 1. see the link startup procedure section for details on waking up the device for different c and starting conditions. to wake up from the local side, send an arbitrary control- channel command to deserializer, wait for 5ms for the chip to power up and then write 0 to sleep register bit to make the wake-up permanent. to wake up from the remote side, enable serialization. the deserializer detects the activity on the serial link and then when it locks, auto- matically sets its sleep register bit to 0. power-down mode the deserializers have a power-down mode which further reduces power consumption compared to sleep mode. set pwdn low to enter power-down mode. in power-down, the parallel outputs remain high impedance. entering power-down resets the devices registers. upon exiting power-down, the state of external pins add[2:0], cx/tp, i2csel, sd/him, and bws are latched. coniguration link the control channel can operate in a low-speed mode called configuration link in the absence of a clock input. this allows a microprocessor to program configuration registers before starting the video link. an internal oscillator provides the clock for the configuration link. set clinken = 1 on the serializer to enable configuration link. configuration link is active until the video link is enabled. the video link overrides the configuration link and attempts to lock when seren = 1. table 12. reverse control-channel modes fast high-immunity mode requires drs = 0. x = dont care. table 13. fast high-immunity mode requirements highimm bit or sd/him pin setting revfast bit reverse control-channel mode max uart/ i 2 c bit rate (kbps) low (1) x legacy reverse control-channel mode (compatible with all gmsl devices) 1000 high (1) 0 high-immunity mode 500 1 fast high-immunity mode 1000 bws setting allowed pclkout frequency (mhz) low > 40 high > 30 open > 80 downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 45 link startup procedure table 14 lists the startup procedure for display applications. table 15 lists the startup procedure for image-sensing applications. the control channel is available after the video link or the configuration link is established. if the deserializer powers up after the serializer, the control channel becomes unavailable for 2ms after power-up. table 14. startup procedure for video-display applications no. c serializer deserializer (autostart enabled) (autostart disabled) c connected to serializer sets all coniguration inputs. if any coniguration inputs are available on one end of the link but not the other, always connects that coniguration input low. sets all coniguration inputs. if any coniguration inputs are available on one end of the link but not the other, always connects that coniguration input low. sets all coniguration inputs. if any coniguration inputs are available on one end of the link but not the other, always connects that coniguration input low 1 powers up powers up and loads default settings. establishes video link when valid pclk available powers up and loads default settings powers up and loads default settings. locks to video link signal if available. 2 enables serial link by setting seren = 1 or coniguration link by setting seren = 0 and clinken = 1 (if valid pclk not available) and gets an acknowledge. waits for link to be establish (~3ms) establishes coniguration or video link locks to coniguration or video link signal 3 writes coniguration bits in the serializer/deserializer and gets an acknowledge. coniguration changed from default settings coniguration changed from default settings 4 if not already enabled, sets seren = 1, gets an acknowledge and waits for video link to be established (~3ms) establishes video link when valid pclk available (if not already enabled) locks to video link signal (if not already locked) 5 begin sending video data to input video data serialized and sent across serial link video data received and deserialized downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 46 table 15. startup procedure for image-sensing applications (cds = high) figure 38. state diagram no. c serializer deserializer (autostart enabled) (autostart disabled) c connected to deserializer sets all coniguration inputs sets all coniguration inputs sets all coniguration inputs 1 powers up powers up and loads default settings. establishes video link when valid pclk available. powers up and loads default settings. goes to sleep after 8ms. powers up and loads default settings. locks to video link signal if available. 2 writes deserializer coniguration bits and gets an acknowledge coniguration changed from default settings 3 wakes up the serializer by sending dummy packet, and then writing sleep = 0 within 8ms. may not get an acknowledge (or gets a dummy acknowledge) if not locked. wakes up 4 writes serializer coniguration bits. may not get an acknowledge (or gets a dummy acknowledge) if not locked. coniguration changed from default settings 5 if not already enabled, sets seren = 1, gets an acknowledge and waits for serial link to be established (~3ms) establishes video link when valid pclk available (if not already enabled) locks to video link signal (if not already locked) 6 begin sending video data to input video data serialized and sent across serial link video data received and deserialized sleep config link operating program registers power-off high to low sleep = 1, video link or config link not locked after 8ms power-on idle wake-up signal serial-port locking signal detected config link unlocked config link locked video link locked video link unlocked 0 sleep 0 sleep all states gpi changes from low to high or pwdn = low or send gpi to gmsl serializer pwdn = high,power-on power-down or power-off serial link activity stops or 8ms elapses after c sets sleep = 1 video link operating prbsen = 0prbsen = 1 video-link prbs test downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 47 high-bandwidth digital content protection (hdcp) note: the explanation of hdcp operation in this data sheet is provided as a guide for general understanding. implementation of hdcp in a product must meet the requirements given in the hdcp system v1.3 amendment for gmsl, which is available from dcp. hdcp has two main phases of operation: authentication and the link integrity check. the c starts authentica - tion by writing to the start_authentication bit in the gmsl serializer. the gmsl serializer generates a 64-bit random number. the host c first reads the 64-bit random number from the gmsl serializer and writes it to the deserializer. the c then reads the gmsl serializer public key selection vector (aksv) and writes it to the deserializer. the c then reads the deserializer ksv (bksv) and writes it to the gmsl serializer. the c begins checking bksv against the revocation list. using the cipher, the gmsl serializer and deserializer calculate a 16-bit response value, r0 and r0, respectively. the gmsl amendment for hdcp reduces the 100ms minimum wait time allowed for the receiver to generate r0 (specified in hdcp rev 1.3) to 128 pixel clock cycles in the gmsl amendment. there are two response-value comparison modes: internal comparison and c comparison. set en_int_ comp = 1 to select internal comparison mode. set en_ int_comp = 0 to select c comparison mode. in internal comparison mode, the c reads the deserializer response r0 and writes it to the gmsl serializer. the gmsl serializer compares r0 to its internally generated response value r0, and sets r0_ri_matched. in c comparison mode, the c reads and compares the r0/r0 values from the gmsl serializer/deserializer. during response-value generation and comparison, the host c checks for a valid bksv (having 20 1s and 20 0s is also reported in bksv_invalid) and checks bksv against the revocation list. if bksv is not on the list and the response values match, the host authenticates the link. if the response values do not match, the c resamples the response values (as described in hdcp rev 1.3, appendix c). if resampling fails, the c restarts authentication by setting the reset_hdcp bit in the gmsl serializer. if bksv appears on the revocation list, the host cannot transmit data that requires protection. the host knows when the link is authenticated and decides when to output data requiring protection. the c performs a link integrity check every 128 frames or every 2s 0.5s. the gmsl serializer/deserializer generate response values every 128 frames. these values are compared internally (internal comparison mode) or can be compared in the host c. in addition, the gmsl serializer/deserializer provide response values for the enhanced link verification. enhanced link verification is an optional method of link verification for faster detection of loss-of-synchronization. for this option, the gmsl serializer and deserializer generate 8-bit enhanced link-verification response values (pj and pj) every 16 frames. the host must detect three consecutive pj/pj mismatches before resampling. encryption enable the gmsl link transfers either encrypted or nonencrypted data. to encrypt data, the host c sets the encryption enable (encryption_enable) bit in both the gmsl serializer and deserializer. the c must set encryption_enable in the same vsync cycle in both the gmsl serializer and deserializer (no internal vsync falling edges between the two writes). the same timing applies when clearing encryption_enable to disable encryption. note: encryption_enable enables/disables encryption on the gmsl irrespective of the content. to comply with hdcp, the c must not allow content requiring encryption to cross the gmsl unencrypted. the c must complete the authentication process before enabling encryption. in addition, encryption must be disabled before starting a new authentication session. synchronization of encryption the video vertical sync (vsync) synchronizes the start of encryption. once encryption has started, the gmsl generates a new encryption key for each frame and each line, with the internal falling edge of vsync and hsync. rekeying is transparent to data and does not disrupt the encryption of video or audio data. repeater support the gmsl serializer/deserializer include features to build an hdcp repeater. an hdcp repeater receives and decrypts hdcp content and then encrypts and transmits on one or more downstream links. a repeater can also use decrypted hdcp content (e.g., to display on a screen). to support hdcp repeater-authentication protocol, the deserializer has a repeater register bit. this register bit must be set to 1 by a c (most likely on the repeater module). both the gmsl serializer and deserializer use sha-1 hash-value calculation over the assembled ksv lists. hdcp gmsl links support a maximum of 15 receivers (total number including the ones in repeater downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 48 modules). if the total number of downstream receivers exceeds 14, the c must set the max_devs_ exceeded register bit when it assembles the ksv list. hdcp authentication procedures the gmsl serializer generates a 64-bit random number exceeding the hdcp requirement. the gmsl serializer/deserializer internal one-time programma - ble (otp) memories contain a unique hdcp keyset programmed at the factory. the host c initiates and controls the hdcp authentication procedure. the gmsl serializer and deserializer generate hdcp authentication response values for the verification of authentication. use the following procedures to authenticate the hdcp gmsl encryption (refer to the hdcp 1.3 amendment for gmsl for details). the c must perform link integrity checks while encryption is enabled (see table 17 ). any event that indicates that the deserializer has lost link synchronization should retrigger authentication. the c must first write 1 to the reset_hdcp bit in the gmsl serializer before starting a new authentication attempt. hdcp protocol summary table 16 , table 17 , and table 18 list the summaries of the hdcp protocol. these tables serve as an implementation guide only. meet the requirements in the gmsl amend- ment for hdcp to be in full compliance. table 16. startup, hdcp authentication, and normal operation (deserializer is not a repeater)first part of the hdcp authentication protocol no. c hdcp gmsl serializer hdcp gmsl deserializer 1 initial state after power-up. powers up waiting for hdcp authentication. powers up waiting for hdcp authentication. 2 makes sure that a/v data not requiring protection (low-value content) is available at the gmsl serializer inputs (such as blue or informative screen). alternatively, uses the force_video and force_audio bits of the gmsl serializer to mask a/v data at the input of the gmsl serializer. starts the link by writing seren = h or link starts automatically if autos is low. 3 starts serialization and transmits low-value content a/v data. locks to incoming data stream and outputs low-value content a/v data. 4 reads the locked bit of the deserializer and makes sure the link is established. 5 optionally writes a random-number seed to the gmsl serializer. combines seed with internally generated random number. if no seed provided, only internal random number is used. 6 if hdcp encryption is required, starts authentication by writing 1 to the start_authentication bit of the gmsl serializer. generates (stores) an, and resets the start_authentication bit to 0. 7 reads an and aksv from the gmsl serializer and writes to the deserializer. generates r0 triggered by the cs write of aksv. 8 reads the bksv and repeater bit from and deserializer writes to the gmsl serializer. generates r0, triggered by the cs write of bksv. downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 49 table 16. startup, hdcp authentication, and normal operation (deserializer is not a repeater)first part of the hdcp authentication protocol (continued) no. c hdcp gmsl serializer hdcp gmsl deserializer 9 reads the invalid_bksv bit of the gmsl serializer and continues with authentication if it is 0. authentication can be restarted if it fails (set reset_hdcp = 1 before restarting authentication). 10 reads r0 from the deserializer and reads r0 from the gmsl serializer. if they match, continues with authentication; otherwise, retries up to two more times (optionally, gmsl serializer comparison can be used to detect if r0/r0 match). authentication can be restarted if it fails (set reset_hdcp = 1 before restarting authentication). 11 waits for the vsync falling edge (internal to the gmsl serializer) and then sets the encryption_enable bit to 1 in the deserializer and gmsl serializer (if the fc is not able to monitor vsync, it can utilize the vsync_det bit in the gmsl serializer). encryption enabled after the next vsync falling edge. decryption enabled after the next vsync falling edge. 12 checks that bksv is not in the key revocation list and continues if it is not. authentication can be restarted if it fails. note: revocation list check can start after bksv is read in step 8. 13 starts transmission of a/v content that needs protection. performs hdcp encryption on high-value content a/v data. performs hdcp decryption on high- value content a/v data. downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 50 table 17. link integrity check (normal)performed every 128 frames after encryption is enabled no. c hdcp gmsl serializer hdcp gmsl deserializer 1 generates ri and updates the ri register every 128 vsync cycles. generates ri and updates the ri register every 128 vsync cycles. 2 continues to encrypt and transmit a/v data. continues to receive, decrypt, and output a/v data. 3 every 128 video frames (vsync cycles) or every 2s. 4 reads ri from the gmsl serializer. 5 reads ri from the deserializer. 6 reads ri again from the gmsl serializer and makes sure it is stable (matches the previous ri that it has read from the gmsl serializer). if ri is not stable, go back to step 5. 7 if ri matches ri, the link integrity check is successful; go back to step 3. 8 if ri does not match ri, the link integrity check fails. after the detection of failure of link integrity check, the fc makes sure that a/v data not requiring protection (low-value content) is available at the gmsl serializer inputs (such as blue or informative screen). alternatively, the force_video and force_audio bits of the gmsl serializer can be used to mask a/v data input of the gmsl serializer. 9 writes 0 to the encryption_enable bit of the gmsl serializer and deserializer. disables encryption and transmits low-value content a/v data. disables decryption and outputs low- value content a/v data. 10 restarts authentication by writing 1 to the reset_hdcp bit followed by writing 1 to the start_authentication bit in the gmsl serializer. downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 51 table 18. optional enhanced link integrity checkperformed every 16 frames after encryption is enabled no. c hdcp gmsl serializer hdcp gmsl deserializer 1 generates pj and updates the pj register every 16 vsync cycles. generates pj and updates the pj register every 16 vsync cycles. 2 continues to encrypt and transmit a/v data. continues to receive, decrypt, and output a/v data. 3 every 16 video frames, reads pj from the gmsl serializer and pj from the deserializer. 4 if pj matches pj, the enhanced link integrity check is successful; go back to step 3. 5 if there is a mismatch, retry up to two more times from step 3. enhanced link integrity check fails after 3 mismatches. after the detection of failure of enhanced link integrity check, the c makes sure that a/v data not requiring protection (low-value content) is available at the gmsl serializer inputs (such as blue or informative screen). alternatively, the force_video and force_audio bits of the gmsl serializer can be used to mask a/v data input of the gmsl serializer. 6 writes 0 to the encryption_enable bit of the gmsl serializer and deserializer. disables encryption and transmits low-value content a/v data. disables decryption and outputs low- value content a/v data. 7 restarts authentication by writing 1 to the reset_hdcp bit followed by writing 1 to the start_authentication bit in the gmsl serializer. downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 52 table 19. hdcp authentication and normal operation (one repeater, two cs)first and second parts of the hdcp authentication protocol example repeater networktwo cs the example shown in figure 39 has one repeater and two cs. table 19 summarizes the authentication operation. figure 39. example network with one repeater and two cs (tx = gmsl serializers, rx = deserializers) no. c_b c_r hdcp gmsl serializer (tx_b1, tx_r1, tx_r2) hdcp gmsl deserializer (rx_r1, rx_d1, rx_d2) tx_b1 cds = 0tx_r1 cds = 0 tx_r2 cds = 0 rx_r1 cds = 1rx_d1 cds = 0 rx_d2 cds = 0 1 initial state after power-up. initial state after power-up. all: power-up waiting for hdcp authentication. all: power-up waiting for hdcp authentication. 2 writes repeater = 1 in rx_r1. retries until proper acknowledge frame received. note: this step must be completed before the irst part of authentication is started between tx_b1 and rx_r1 by the c_b (step 7). for example, to satisfy this requirement, rx_r1 can be held at power-down until c_r is ready to write the repeater bit, or c_b can poll c_r before starting authentication. ?e ?e ?? ? ? ? ?? ?? e yt ? ? rx_d1 display 2 rx_d2 repeater tx_r1 tx_r2 rx_r 2 c_r video routing memory with srm video connection control connection 1 (c_b in bd-drive is master) control connection 2 (c_r in repeater is master) downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 53 table 19. hdcp authentication and normal operation (one repeater, two cs)first and second parts of the hdcp authentication protocol (continued) no. c_b c_r hdcp gmsl serializer (tx_b1, tx_r1, tx_r2) hdcp gmsl deserializer (rx_r1, rx_d1, rx_d2) tx_b1 cds = 0tx_r1 cds = 0 tx_r2 cds = 0 rx_r1 cds = 1rx_d1 cds = 0 rx_d2 cds = 0 3 makes sure that a/v data not requiring protection (low- value content) is available at the tx_b1 inputs (such as blue or informative screen). alternatively, the force_ video and force_audio bits of tx_b1 can be used to mask a/v data input of tx_b1. starts the link between tx_b1 and rx_r1 by writing seren = h to tx_b1, or link starts automatically if autos is low. tx_b1: starts serialization and transmits low-value content a/v data. rx_r1: locks to incoming data stream and outputs low-value content a/v data. 4 starts all downstream links by writing seren = h to tx_r1, tx_r2, or links start automatically if autos of transmitters are low. tx_r1, tx_r2: starts serialization and transmits low-value content a/v data. rx_d1, rx_d2: locks to incoming data stream and outputs low-value content a/v data. 5 reads the locked bit of rx_r1 and makes sure the link between tx_b1 and rx_r1 is established. reads the locked bit of rx_d1 and makes sure the link between tx_r1 and rx_d1 is established. reads the locked bit of rx_d2 and makes sure the link between tx_r2 and rx_d2 is established. 6 optionally, writes a random number seed to tx_b1. writes 1 to the gpio_0_function and gpio_1_function bits in rx_r1 to change gpio functionality used for hdcp purpose. optionally, writes a random-number seed to tx_r1 and tx_r2. 7 starts and completes the irst part of the authentication protocol between tx_b1, rx_r1 (see steps 6C10 in table 16). tx_b1: according to commands from c_b, generates an, computes r0. rx_r1: according to commands from c_b, computes r0. downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 54 table 19. hdcp authentication and normal operation (one repeater, two cs)first and second parts of the hdcp authentication protocol (continued) no. c_b c_r hdcp gmsl serializer (tx_b1, tx_r1, tx_r2) hdcp gmsl deserializer (rx_r1, rx_d1, rx_d2) tx_b1 cds = 0tx_r1 cds = 0 tx_r2 cds = 0 rx_r1 cds = 1rx_d1 cds = 0 rx_d2 cds = 0 8 when gpio_1 = 1 is detected, starts and completes the irst part of the authentication protocol between the (tx_r1, rx_d1) and (tx_r2, rx_d2) links (see steps 6C10 in table 16). tx_r1, tx_r2: according to commands from c_r, generates an, computes r0. rx_d1, rx_d2: according to commands from c_r, computes r0. 9 waits for the vsync falling edge and then enables encryption on the (tx_b1, rx_r1) link. full authentication is not complete yet so it makes sure a/v content that needs protection is not transmitted. since repeater = 1 was read from rx_r1, the second part of authentication is required. tx_b1: encryption enabled after next vsync falling edge. rx_r1: decryption enabled after next vsync falling edge. 10 when gpio_0 = 1 is detected, enables encryption on the (tx_r1, rx_d1) and (tx_r2, rx_d2) links. tx_r1, tx_r2: encryption enabled after next vsync falling edge. rx_d1, rx_d2: decryption enabled after next vsync falling edge. 11 waits for some time to allow c_r to make the ksv list ready in rx_r1. then polls (reads) the ksv_list_ready bit of rx_r1 regularly until proper acknowledge frame is received and bit is read as 1. blocks control channel from c_b side by setting revccen = fwdccen = 0 in rx_r1. retries until proper acknowledge frame received. rx_r1: control channel from serializer side (tx_b1) is blocked after fwdccen = revccen = 0 is written. 12 writes bksvs of rx_d1 and rx_d2 to the ksv list in rx_ r1. then, calculates and writes the binfo register of rx_r1. rx_r1: triggered by c_rs write of binfo, calculates hash value (v) on the ksv list, binfo and the secret- value m0. 13 writes 1 to the ksv_list_ ready bit of rx_r1 and then unblocks the control channel from the c_b side by setting revccen = fwdccen = 1 in rx_r1. rx_r1: control channel from the serializer side (tx_b1) is unblocked after fwdccen = revccen = 1 is written. downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 55 table 19. hdcp authentication and normal operation (one repeater, two cs)first and second parts of the hdcp authentication protocol (continued) detection and action upon new device connection when a new device is connected to the system, the device must be authenticated and the devices ksv checked against the revocation list. the downstream cs can set the new_dev_conn bit of the upstream receiver and invoke an interrupt to notify upstream cs. notiication of start of authentication and enable of encryption to downstream links hdcp repeaters do not immediately begin authentication upon startup or detection of a new device, but instead wait for an authentication request from the upstream transmitter/repeaters. use the following procedure to notify downstream links of the start of a new authentication request: 1) host c begins authentication with the hdcp repeaters input receiver. 2) when aksv is written to hdcp repeaters input receiver, its auth_started bit is automatically set and its gpio1 goes high (if gpio1_function is set to high). 3) hdcp repeaters c waits for a low-to-high transition on hdcp repeater input receivers auth_started bit and/or gpio1 (if configured) and starts authentication downstream. 4) hdcp repeaters c resets the auth_started bit. no. c_b c_r hdcp gmsl serializer (tx_b1, tx_r1, tx_r2) hdcp gmsl deserializer (rx_r1, rx_d1, rx_d2) tx_b1 cds = 0tx_r1 cds = 0 tx_r2 cds = 0 rx_r1 cds = 1rx_d1 cds = 0 rx_d2 cds = 0 14 reads the ksv list and binfo from rx_r1 and writes them to tx_b1. if any of the max_ devs_exceeded or max_ cascade_exceeded bits is 1, then authentication fails. note: binfo must be written after the ksv list. tx_b1: triggered by c_bs write of binfo, calculates hash value (v) on the ksv list, binfo and the secret- value m0. 15 reads v from tx_b1 and v from rx_r1. if they match, continues with authentication; otherwise, retries up to two more times. 16 searches for each ksv in the ksv list and bksv of rx_r1 in the key revocation list. 17 if keys are not revoked, the second part of the authentication protocol is completed. 18 starts transmission of a/v content that needs protection. all: perform hdcp encryption on high- value a/v data. all: perform hdcp decryption on high- value a/v data. downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 56 set gpio0_function to high to have gpio0 follow the encryption_enable bit of the receiver. the repeater c can use this function for notification when encryption is enabled/disabled by an upstream c. applications information self prbs test the serializers include a prbs pattern generator which works with bit-error verification in the deserializer. to run the prbs test, disable encryption (if used), set dishsfilt, disvsfilt, and disdefilt to 1, to disable glitch filter in the deserializer. then, set prbsen = 1 (0x04, d5) in the serializer and then in the deserializer. to exit the prbs test, set prbsen = 0 (0x04, d5) in the deserializer and then in the serializer. error checking the deserializers check the serial link for errors and store the number of decoding errors in the 8-bit registers decerr (0x0d). if a large number of decoding errors are detected within a short duration (error rate 1/4), the deserializers lose lock and stop the error counter. the deserializers then attempt to relock to the serial data. decerr reset upon successful video link lock, successful readout of the register (through c), or whenever auto error reset is enabled. the deserializers use a separate prbs register during the internal prbs test, and decerr are reset to 0x00. err output the deserializers have an open-drain err output. this output asserts low whenever the number of decoding errors exceeds the error thresholds during normal operation, or when at least 1 prbs error is detected during prbs test. err reasserts high whenever decerr resets, due to decerr readout, video link lock, or auto error reset. auto error reset the default method to reset errors is to read the respective error registers in the deserializers (0x0d and 0x0e). auto error reset clears the error counters decerr and the err output ~1s after err goes low. auto error reset is disabled on power-up. enable auto error reset through autorst (0x06, d5). auto error reset does not run when the device is in prbs test mode. dual c control usually systems have one microcontroller to run the control channel, located on the serializer side for display applications or on the deserializer side for image-sensing applications. however, a c can reside on each side simultaneously, and trade off running the control channel. in this case, each c can communicate with the serializer and deserializer and any peripheral devices. contention will occur if both cs attempt to use the control channel at the same time. it is up to the user to prevent this contention by implementing a higher level protocol. in addition, the control channel does not provide arbitration between i 2 c masters on both sides of the link. an acknowledge frame is not generated when communication fails due to contention. if communication across the serial link is not required, the cs can disable the forward and reverse control channel using the fwdccen and revccen bits (0x04, d[1:0]) in the serializer/deserializer. communication across the serial link is stopped and contention between cs cannot occur. as an example of dual c use in an image-sensing application, the serializer can be in sleep mode and waiting for wake-up by c on the deserializer side. after wake- up, the serializer-side c assumes master control of the serializers registers. changing the clock frequency it is recommended that the serial link be enabled after the video clock (f pclkout ) and the control-channel clock (f uart /f i2c ) are stable. when changing the clock frequency, stop the video clock for 5s, apply the clock at the new frequency, then restart the serial link or toggle seren. on-the-fly changes in clock frequency are possible if the new frequency is immediately stable and without glitches. the reverse control channel remains unavailable for 500s after serial link start or stop. when using the uart interface, limit on-the-fly changes in f uart to factors of less than 3.5 at a time to ensure that the device recognizes the uart sync pattern. for example, when lowering the uart frequency from 1mbps to 100kbps, first send data at 333kbps then at 100kbps for reduction ratios of 3 and 3.333, respectively. fast detection of loss-of-synchronization a measure of link quality is the recovery time from loss-of-synchronization. the host can be quickly notified of loss-of-lock by connecting the deserializers lock output to the gpi input. if other sources use the gpi input, such as a touch-screen controller, the c can implement a routine to distinguish between interrupts from loss- of-sync and normal interrupts. reverse control-channel communication does not require an active forward link to operate and accurately tracks the lock status of the gmsl link. lock asserts for video link only and not for the configuration link. downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 57 providing a frame sync (camera applications) the gpi/gpo provide a simple solution for camera applications that require a frame sync signal from the ecu (e.g. surround-view systems). connect the ecu frame sync signal to the gpi input, and connect gpo output to the camera frame sync input. gpi/gpo has a typical delay of 275s. skew between multiple gpi/ gpo channels is typically 115s. if a lower skew signal is required, connect the cameras frame sync input one of the deserializers gpios and use an i 2 c broadcast write command to change the gpio output state. this has a maximum skew of 1.5s, independent from the used i 2 c bit rate. software programming of the device addresses the serializers and deserializers have programmable device addresses. this allows multiple gmsl devices, along with i 2 c peripherals, to coexist on the same control channel. the serializer device address is in register 0x00 of each device, while the deserializer device address is in register 0x01 of each device. to change a device address, first write to the device whose address changes (register 0x00 of the serializer for serializer device address change, or register 0x01 of the deserializer for deserializer device address change). then write the same address into the corresponding register on the other device (register 0x00 of the deserializer for serializer device address change, or register 0x01 of the serializer for deserializer device address change). 3-level coniguration inputs cx/tp and bws are 3-level inputs that control the serial interface configuration and power-up defaults. connect 3-level inputs through a pullup resistor to iovdd to set a high level, a pulldown resistor to gnd to set a low level, or open to set a mid level. for digital control, use three-state logic to drive the 3-level logic input. coniguration blocking the deserializers can block changes to registers. set cfgblock to make registers 0x00 to registers 0x1f as read only. once set, the registers remain blocked until the supplies are removed or until pwdn is low. compatibility with other gmsl devices the deserializers are designed to pair with the max9275C max9281 serializers but interoperates with any gmsl serializers. see the table 20 for operating limitations key memory each device has a unique hdcp key set that is stored in secure nonvolatile memory (nvm). the hdcp key set consists of forty 56-bit private keys and one 40-bit public key. the nvm is qualified for automotive applications. hs/vs/de inversion the deserializer uses an active-high hs, vs, and de for encoding and hdcp encryption. set invhsync, invvsync, and invde in the serializer (registers 0x0d, 0x0e) to invert active-low input signals for use with the gmsl devices. set invhsync, invvsync, and invde in the deserializer (register 0x0e) to output active-low signals for use with downstream devices. ws/sck inversion the deserializer uses standard polarities for i 2 s. set invws, invsck in the serializer (register 0x1b) to invert opposite polarity signals for use with the gmsl devices. set invws, invsck in the deserializer (register 0x1d) to output reverse-polarity signals for downstream use. table 20. max9276a/max9280a feature compatibility max9276a/max9280a feature gmsl serializer hdcp (max9280a only) if feature not supported in serializer, must not be turned on in the max9280a high-bandwidth mode if feature not supported in serializer, must only use 24-bit and 32-bit modes i 2 c to i 2 c if feature not supported in serializer, must use uart to i 2 c or uart to uart coax if feature not supported in serializer, must connect unused serial output through 200nf and 50 in series to v dd and set the reverse control-channel amplitude to 100mv. high-immunity control channel if feature not supported in serializer, must use the legacy reverse con trol-channel modetdm encoding if feature not supported in serializer, must use i 2 s encoding (with 50% ws duty cycle), if supported i 2 s encoding if feature not supported in serializer must disable i 2 s in the max9276a/max9280a downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 58 gpios the deserializers have two open-drain gpios available when not used for hdcp purposes (see the notification of start of authentication and enable of encryption to downstream links section), gpio1out and gpio0out (0x06, d3 and d1) set the output state of the gpios. setting the gpio output bits to 0 low pulls the output low, while setting the bits to 1 leaves the output undriven, and pulled high through internal/external pullup resistors. the gpio input buffers are always enabled. the input states are stored in gpio1 and gpio0 (0x06, d2 and d0). set gpio1out/gpio0out to 1 when using gpio1/gpio0 as an input. staggered parallel outputs the deserializers stagger the parallel data outputs to reduce emi and noise. staggering outputs also reduces the power-supply transient requirements. by default, the deserializers stagger outputs according to table 21 . disable output staggering through the disstag bit (0x06, d7). internal input pulldowns the control and configuration inputs (except 3-level inputs) include a pulldown resistor to gnd. external pulldown resistors are not needed. choosing i 2 c/uart pullup resistors i 2 c and uart open-drain lines require a pullup resistor to provide a logic-high level. there are tradeoffs between power dissipation and speed, and a compromise may be required when choosing pullup resistor values. every device connected to the bus introduces some capacitance even when the device is not in operation. i 2 c specifies 300ns rise times (30% to 70%) for fast mode, which is defined for data rates up to 400kbps (see the i 2 c specifications in the ac electrical characteristics table for details). to meet the fast-mode rise-time requirement, choose the pullup resistors so that rise time t r = 0.85 x r pullup x c bus < 300ns. the waveforms are not recognized if the transition time becomes too slow. the device supports i 2 c/uart rates up to 1mbps. ac-coupling ac-coupling isolates the receiver from dc voltages up to the voltage rating of the capacitor. capacitors at the serializer output and at the deserializer input are needed for proper link operation and to provide protection if either end of the cable is shorted to a battery. ac-coupling blocks low-frequency ground shifts and low-frequency common-mode noise. selection of ac-coupling capacitors voltage droop and the digital sum variation (dsv) of transmitted symbols cause signal transitions to start from different voltage levels. because the transition time is fixed, starting the signal transition from different voltage levels causes timing jitter. the time constant for an ac-coupled link needs to be chosen to reduce droop and jitter to an acceptable level. the rc network for an ac-coupled link consists of the cml/coax receiver termination resistor (r tr ), the cml/coax driver termination resistor (r td ), and the series ac-coupling capacitors (c). the rc time constant for four equal-value series capacitors is (c x (r td + r tr ))/4. r td and r tr are required to match the transmission line impedance (usually 100 differential, 50 single ended). this leaves the capacitor selection to change the system time constant. use at 0.22f (using legacy reverse control channel), 47nf (using high-immunity reverse control channel), or larger high-frequency surface-mount ceramic capacitors, with sufficient voltage rating to withstand a short to battery, to pass the lower speed reverse control-channel signal. use capacitors with a case size less than 3.2mm x 1.6mm to have lower parasitic effects to the high-speed signal. power-supply circuits and bypassing the deserializers use an avdd and dvdd of 3.0v to 3.6v. all single-ended inputs and outputs except for the serial input derive power from an iovdd of 1.7v to 3.6v, which scale with iovdd. proper voltage-supply bypass- ing is essential for high-frequency circuit stability. table 21. staggered output delay output output delay relative to dout0 (ns) disstag = 0 disstag = 1 dout0Cdout5, dout21, dout22 0 0 dout6Cdout10, dout23, dout24 0.5 0 dout11Cdout15, dout25, dout26 1 0 dout16Cdout20, dout27, dout28 1.5 0 pclkout 0.75 0 downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 59 power-supply table power-supply currents shown in the dc electrical characteristics table is the sum of the currents from avdd, dvdd, and iovdd. iovdd is measured at v iovdd = 3.6v. if using a different iovdd voltage, the iovdd worst-case supply current will vary according to table 22 . hdcp operation (max9280a only) draws addi- tional current. this is shown in table 23 . cables and connectors interconnect for cml typically has a differential imped- ance of 100. use cables and connectors that have matched differential impedance to minimize impedance discontinuities. coax cables typically have a characteristic impedance of 50, contact the factory for 75 operation). table 24 lists the suggested cables and connectors used in the gmsl link. table 24. suggested connectors and cables for gmsl table 22. iovdd current simulation results table 23. additional supply current from hdcp (max9280a only) vendor connector cable type rosenberger 59s2ax-400a5-y rg174 coax rosenberger d4s10a-40ml5-z dacar 538 stp nissei gt11l-2s f-2wme awg28 stp jae mx38-ff a-bw-lxxxxx stp iovdd worst-case supply current iovdd supply voltage 1.9v 3.3v* 3.6v bws = low, f pclkout = 16.6mhz c l = 5pf 4.4 7.9 8.6 ma c l = 10pf 6.4 12.4 13.5 bws = low, f pclkout = 33.3mhz c l = 5pf 8 14.5 15.8 c l = 10pf 13.2 23.1 25.2 bws = low, f pclkout = 66.6mhz c l = 5pf 14.9 25.6 27.9 c l = 10pf 23.4 40.7 44.4 bws = low, f pclkout = 104mhz c l = 5pf 21.6 38.7 42.2 c l = 10pf 34.8 60.3 65.8 bws = mid, f pclkout = 36.6mhz c l = 5pf 10.2 18.2 19.8 c l = 10pf 16.6 28.9 31.5 bws = mid, f pclkout = 104mhz c l = 5pf 25.1 45 49 c l = 10pf 40.4 70.2 76.5 pclk (mhz) maximum hdcp current (ma) 16.6 6 33.3 9 36.6 9 66.6 12 104 18 downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 60 board layout separate lvcmos logic signals and cml/coax high- speed signals to prevent crosstalk. use a four-layer pcb with separate layers for power, ground, cml/coax, and lvcmos logic signals. layout pcb traces close to each other for a 100 differential characteristic impedance for stp. the trace dimensions depend on the type of trace used (microstrip or stripline). note that two 50 pcb traces do not have 100 differential impedance when brought close togetherthe impedance goes down when the traces are brought closer. use a 50 trace for the single-ended output when driving coax. route the pcb traces for differential cml channel in par- allel to maintain the differential characteristic impedance. avoid vias. keep pcb traces that make up a differential pair equal length to avoid skew within the differential pair. esd protection esd tolerance is rated for human body model, iec 61000-4-2, and iso 10605. the iso 10605 and iec 61000-4-2 standards specify esd tolerance for electronic systems. the serial link inputs are rated for iso 10605 esd protection and iec 61000-4-2 esd protection. all pins are tested for the human body model. the human body model discharge components are c s = 100pf and r d = 1.5k ( figure 40 ). the iec 61000-4-2 discharge components are c s = 150pf and r d = 330 ( figure 41 ). the iso 10605 discharge components are c s = 330pf and r d = 2k ( figure 42 ). figure 40. human body model esd test circuit figure 41. iec 61000-4-2 contact discharge esd test circuit figure 42. iso 10605 contact discharge esd test circuit a ???? f storage ca pa ci to r high- vol ta ge dc source device under test charge-current- limit resistor discharge resistance r d 330 ? orage ca pa ci to r high- vol ta ge dc source device under test charge-curren t- limit resis to r discharge resistance 1m r d 1.5k c s 100pf orage ca pa ci to r high- vol ta ge dc source device under test charge-current- limit resistor discharge resistance r d ? ? ? ee? downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 61 table 25. register table (see table 26 ) register address bits name value function default value 0x00 d[7:1] serid xxxxxxx serializer device address (power-up default value depends on latched address pin level) xx00xx0 d0 0 reserved 0 0x01 d[7:1] desid xxxxxxx deserializer device address (power-up default value depends on latched address pin level) xx01xxx d0 cfgblock 0 normal operation 0 1 registers 0x00 to 0x1f are read only 0x02 d[7:6] ss 00 no spread spectrum 00 01 2% spread spectrum 10 no spread spectrum 11 4% spread spectrum d5 audiomode 0 ws, sck conigured as output (deserializer sourced clock) 0 1 ws, sck conigured as input (system sourced clock) d4 audioen 0 disable i 2 s/tdm channel 1 1 enable i 2 s/tdm channel d[3:2] prng 00 12.5mhz to 25mhz pixel clock 11 01 25mhz to 50mhz pixel clock 10 50mhz to 104mhz pixel clock 11 automatically detect the pixel clock range d[1:0] srng 00 0.5 to 1gbps serial-data rate 11 01 1 to 2gbps serial-data rate 10 2 to 3.12gbps serial-data rate 11 automatically detect serial-data rate 0x03 d[7:6] autofm 00 calibrate spread modulation rate only once after locking 00 01 calibrate spread-modulation rate every 2ms after locking 10 calibrate spread-modulation rate every 16ms after locking 11 calibrate spread-modulation rate every 256ms after locking d5 0 reserved 0 d[4:0] sdiv 00000 auto calibrate sawtooth divider 00000 xxxxx manual sdiv setting (see the manual programming of the spread-spectrum divider section) downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 62 table 25. register table (see table 26 ) (continued) register address bits name value function default value 0x04 d7 locked 0 lock output is low 0 (read only) 1 lock output is high d6 outenb 0 enable outputs (power-up default value depends on enable pin value at power-up) 0, 1 1 disable outputs (power-up default value depends on enable pin value at power-up) d5 prbsen 0 disable prbs test 0 1 enable prbs test d4 sleep 0 normal mode (power-up default value depends on ms pin value at power-up) 0, 1 1 activate sleep mode (power-up default value depends on ms pin value at power-up) d[3:2] inttype 00 local control channel uses i 2 c when i2csel = 0 01 01 local control channel uses uart when i2csel = 0 10, 11 local control channel disabled d1 revccen 0 disable reverse control channel to serializer (sending) 1 1 enable reverse control channel to serializer (sending) d0 fwdccen 0 disable forward control channel from serializer (receiving) 1 1 enable forward control channel from serializer (receiving) 0x05 d7 i2cmethod 0 i 2 c conversion sends the register address when converting uart to i 2 c 0 1 disable sending of i 2 c register address when converting uart to i 2 c (command-byte-only mode) d[6:5] hpftune 00 7.5mhz equalizer highpass-ilter cutoff frequency 01 01 3.75mhz equalizer highpass-ilter cutoff frequency 10 2.5mhz equalizer highpass-ilter cutoff frequency 11 1.87mhz equalizer highpass-ilter cutoff frequency d4 pdeq 0 enable equalizer 0 1 disable equalizer d[3:0] eqtune 0000 2.1db equalizer boost gain 1001 0001 2.8db equalizer boost gain 0010 3.4db equalizer boost gain 0011 4.2db equalizer boost gain 0100 5.2db equalizer boost gain 0101 6.2db equalizer boost gain 0110 7db equalizer boost gain 0111 8.2db equalizer boost gain 1000 9.4db equalizer boost gain 1001 10.7db equalizer boost gain. power-up default. 1010 11.7db equalizer boost gain 1011 13db equalizer boost gain 11xx do not use downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 63 table 25. register table (see table 26 ) (continued) register address bits name value function default value 0x06 d7 disstag 0 enable staggered outputs 0 1 disable staggered outputs d6 autorst 0 do not automatically reset error registers and outputs 0 1 automatically reset decerr register 1s after err asserts d5 disgpi 0 enable gpi-to-gpo signal transmission to serializer 0 1 disable gpi-to-gpo signal transmission to serializer d4 gpiin 0 gpi input is low 0 (read only) 1 gpi input is high d3 gpio1out 0 set gpio1 to low 1 1 set gpio1 to high d2 gpio1in 0 gpio1 input is low 0 (read only) 1 gpio1 input is high d1 gpio0out 0 set gpio0 to low 1 1 set gpio0 to high d0 gpio0in 0 gpio0 input is low 0 (read only) 1 gpio0 input is high 0x07 d[7:0] 01010100 reserved 01010100 0x08 d[7:3] 00110 reserved 00110 d2 disdefilt 0 enable de glitch ilter 0 1 disable de glitch ilter d1 disvsfilt 0 enable vs glitch ilter 0 1 disable vs glitch ilter d0 dishsfilt 0 enable hs glitch ilter 0 1 disable hs glitch ilter 0x09 d[7:0] 11001000 reserved 11001000 0x0a d[7:0] 00010xxx reserved 00010xxx 0x0b d[7:0] 00100000 reserved 00100000 0x0c d[7:0] errthr xxxxxxxx error threshold for decoding errors 00000000 0x0d d[7:0] decerr xxxxxxxx decoding error counter 00000000 (read only) 0x0e d[7:0] prbserr xxxxxxxx prbs error counter 00000000 (read only) 0x0f d[7:0] xxxxxxxx reserved (read only) 0x10 d[7:0] xxxxxxxx reserved (read only) 0x11 d7 revfast 0 high-immunity reverse channel mode uses 500kbps bit rate 0 1 high-immunity reverse channel mode uses 1mbps bit rate d[6:0] 0100010 reserved 0100010 downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 64 table 25. register table (see table 26 ) (continued) register address bits name value function default value 0x12 d7 mclksrc 0 mclk derived from pclkout (see table 5) 0 1 mclk derived from internal oscillator d[6:0] mclkdiv 0000000 mclk disabled 0000000 xxxxxxx mclk divider 0x13 d[7:0] 0x000000 reserved 0x000000 0x14 d7 invvsync 0 no vs inversion at the output 0 1 invert vs at the output d6 invhsync 0 no hs inversion at the output 0 1 invert hs at the output d5 invde 0 no de inversion at the output 0 1 invert de at the output d4 drs 0 high data-rate mode 0 1 low data-rate mode d3 dcs 0 normal parallel-output-driver current 0 1 boosted parallel-output-driver current d2 disrwake 0 enable remote wake-up 0 1 disable remote wake-up d1 es 0 output data valid on rising edge of pclkout 0 1 output data valid on falling edge of pclkout d0 intout 0 drive intout low 0 1 drive intout high 0x15 d7 autoint 0 intout pin output controlled by intout bit above 1 1 writes to any avinfo bytes sets intout to high. reads to any avinfo bytes sets intout to low d6 hvtren 0 disable hs/vs tracking (power-up default value depends on state of bws input value at power-up) 0, 1 1 enable hs/vs tracking (power-up default value depends on state of bws input value at power-up) d5 detren 0 disable de tracking (power-up default value depends on state of bws input value at power-up) 0, 1 1 enable de tracking (power-up default value depends on state of bws input value at power-up) d4 hvtrmode 0 partial periodic hs/vs and de tracking 1 1 partial and full periodic hs/vs and de tracking d[3:2] 00 reserved 00 d1 mclkws 0 mclk output operates normally 0 1 ws is output from mclk (mclk mirrors ws) d0 mclkpin 0 mclk output on dout28/cntl2 0 1 mclk output on cntl0/add0 downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 65 table 25. register table (see table 25 ) (continued) register address bits name value function default value 0x16 d7 highimm 0 legacy reverse control-channel mode (power-up default value depends on sd/him at power-up) 0, 1 1 high-immunity reverse control-channel mode (power-up default value depends on sd/him at power-up) d[6:0] 1011010 reserved 1011010 0x17 d[7:0] 000xxxxx reserved 000xxxxx 0x18 d[7:1] i2csrca xxxxxxx i 2 c address translator source a 0000000 d0 0 reserved 0 0x19 d[7:1] i2cdsta xxxxxxx i 2 c address translator destination a 0000000 d0 0 reserved 0 0x1a d[7:1] i2csrcb xxxxxxx i 2 c address translator source b 0000000 d0 0 reserved 0 0x1b d[7:1] i2cdstb xxxxxxx i 2 c address translator destination b 0000000 d0 0 reserved 0 0x1c d7 i2clocack 0 acknowledge not generated when forward channel is not available 1 1 i 2 c-to-i 2 c slave generates local acknowledge when forward channel is not available d[6:5] i2cslvsh 00 352ns/117ns i 2 c setup/hold time 01 01 469ns/234ns i 2 c setup/hold time 10 938ns/352ns i 2 c setup/hold time 11 1046ns/469ns i 2 c setup/hold time d[4:2] i2cmstbt 000 8.47kbps (typ) i 2 c-to-i 2 c master bit-rate setting 101 001 28.3kbps (typ) i 2 c-to-i 2 c master bit-rate setting 010 84.7kbps (typ) i 2 c-to-i 2 c master bit-rate setting 011 105kbps (typ) i 2 c-to-i 2 c master bit-rate setting 100 173kbps (typ) i 2 c-to-i 2 c master bit-rate setting 101 339kbps (typ) i 2 c-to-i 2 c master bit-rate setting 110 533kbps (typ) i 2 c-to-i 2 c master bit-rate setting 111 837kbps (typ) i 2 c-to-i 2 c master bit-rate setting d[1:0] i2cslvto 00 64s (typ) i 2 c-to-i 2 c slave remote timeout 10 01 256s (typ) i 2 c-to-i 2 c slave remote timeout 10 1024s (typ) i 2 c-to-i 2 c slave remote timeout 11 no i 2 c-to-i 2 c slave remote timeout 0x1d d[7:3] 00000 reserved 00000 d2 audufbeh 0 audio fifo repeats last audio word when fifo is empty 0 1 audio fifo outputs all zeros when fifo is empty d1 invsck 0 do not invert sck at output 0 1 invert sck at output d0 invws 0 do not invert ws at output 0 1 invert ws at output downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 66 table 25. register table (see table 26 ) (continued) x = dont care. register address bits name value function default value 0x1e d[7:0] id 00100x10 device identiier (max9276a = 0x22) (max9280a = 0x26) 00100x10 (read only) 0x1f d[7:5] 000 reserved 000 (read only) d4 caps 0 not hdcp capable (max9276a) (read only) 1 hdcp capable (max9280a) d[3:0] revision xxxx device revision (read only) 0x40 to 0x59 d[7:0] avinfo xxxxxxxx audio/video format/status/information bytes all zeroes 0x77 d[7:0] xxxxxxxx (read only) 0x78 d[7:0] audouper xxxxxxxx audio fifo last overlow/underlow period (audiomode = 1 only) (read only) 0x79 d7 audou 0 audio fifo is in underlow (audiomode = 1 only) (read only) 1 audio fifo is in overlow (audiomode = 1 only) d[6:0] 0000xxx reserved 0000xxx (read only) 0x7b d[7:0] lutaddr xxxxxxxx lut start address for write and read 00000000 0x7c d[7:4] 0000 reserved 0000 d3 lutprog 0 disable lut write and read 0 1 enable lut write and read d2 bluluten 0 disable blue lut 0 1 enable blue lut d1 grnluten 0 disable green lut 0 1 enable green lut d0 redluten 0 disable red lut 0 1 enable red lut 0x7d d[7:0] redlut xxxxxxxx red lut value (see table 11) 00000000 0x7e d[7:0] greenlut xxxxxxxx green lut value (see table 11) 00000000 0x7f d[7:0] bluelut xxxxxxxx blue lut value (see table 11) 00000000 downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 67 table 26. hdcp register table (max9280a only, see table 25 ) register address size (bytes) name read/ write function default value (hex) 0x80 to 0x84 5 bksv read only hdcp receiver ksv (read only) 0x85 to 0x86 2 ri read only link veriication response (read only) 0x87 1 pj read only enhanced link veriication response (read only) 0x88 to 0x8f 8 an read/write session random number 0x0000000000000000 0x90 to 0x94 5 aksv read/write hdcp transmitter ksv 0x0000000000 0x95 1 bctrl read/write d7 = pd_hdcp 1 = power down hdcp circuits 0 = hdcp circuits normal 0x00 d[6:4] = reservedd3 = gpio1_function 1 = gpio1 mirrors auth_started 0 = normal gpio1 operation d2 = gpio0_function 1 = gpio0 mirrors encryption_enable 0 = normal gpio0 operation d1 = auth_started 1 = authentication started (triggered by write to aksv) 0 = authentication not started d0 = encryption_enable 1 = enable encryption 0 = disable encryption 0x96 1 bstatus read/write d[7:2] = reserved 0x00 d1 = new_dev_conn1 = set to 1 if a new connected device is detected 0 = set to 0 if no new device is connected d0 = ksv_list_ready 1 = set to 1 if ksv list and binfo is ready 0 = set to 0 if ksv list or binfo is not ready 0x97 1 bcaps read/write d[7:1] = reserved 0x00 d0 = repeater 1 = set to one if device is a repeater 0 = set to zero if device is not a repeater 0x98 to 0x9f 8 read only reserved 0x0000000000000000 (read only) 0xa0 to 0xa3 4 v.h0 read/write h0 part of sha-1 hash value 0x00000000 0xa4 to 0xa7 4 v.h1 read/write h1 part of sha-1 hash value 0x00000000 0xa8 to 0xab 4 v.h2 read/write h2 part of sha-1 hash value 0x00000000 0xac to 0xaf 4 v.h3 read/write h3 part of sha-1 hash value 0x00000000 0xb0 to 0xb3 4 v.h4 read/write h4 part of sha-1 hash value 0x00000000 downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 68 table 26. hdcp register table (max9280a only, see table 25 ) (continued) register address size (bytes) name read/ write function default value (hex) 0xb4 to 0xb5 2 binfo read/write d[15:12] = reserved 0x0000 d11 = max_cascade_exceeded 1 = set to one if more than seven cascaded devices attached 0 = set to zero if seven or fewer cascaded devices attached d[10:8] = depth depth of cascaded devices d7 = max_devs_exceeded 1 = set to one if more than 14 devices attached 0 = set to zero if 14 or fewer devices attached d[6:0] = device_count number of devices attached 0xb6 1 gpmem read/write general-purpose memory byte 0x00 0xb7 to 0xb9 3 read only reserved 0x000000 0xba to 0xff 70 ksv_list read/write list of ksvs downstream repeaters and receivers (maximum of 14 devices) all zeros downloaded from: http:///
max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output www.maximintegrated.com maxim integrated 69 typical application circuit ordering information note: all devices operate over the -40 c to +105 c temperature range. /v denotes an automotive qualified part. +denotes a lead(pb)-free/rohs-compliant package. *future product contact factory for availability. **ep = exposed pad. ***hdcp parts require registration with digital content protection, llc. chip information process: cmos package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. part pin-package hdcp max9276a ggn/vy+* 56 qfnd-ep** no max9276agtn+ 56 tqfn-ep** no max9276agtn/v+ 56 tqfn-ep** no max9280a gtn+ 56 tqfn-ep** yes*** max9280agtn/v+ 56 tqfn-ep** yes*** package type package code outline no. land pattern no. 56 tqfn-ep t5688+2 21-0135 90-0046 56 qfnd-ep g5688y+1 21-0704 90-0423 pclk rgbhv gpu ecu uart tx rx int ims audio ws sck sd pclkindin(26:0) cds/cntl3 lmn0 lmn1 out- conf3conf2 conf0 conf1 out+ rx/sda tx/scl gpo/him ws ms/cntlosd sck sclsda pclkout dout(26:0) i2csel int rx/sda tx/scl lock in+ intout/add2 cntl3/add1 cntl0/add0in- ws sd/him sck dout28/mclk 4.99k 4.99k 45.3k 45.3k 49.9k 49.9k wssd sckmclk pclkrgb to peripherals display max9850 max9276amax9280a max9275max9279 note: no t al l pullup/pulldown resistors are shown. see pin description for de ta ils. video-displa y application lflt lflt cx/tp downloaded from: http:///
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and speciications without n otice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. max9276a/max9280a 3.12gbps gmsl deserializers for coax or stp input and parallel output ? 2016 maxim integrated products, inc. 70 revision history revision number revision date description pages changed 0 1/16 initial release for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com. downloaded from: http:///

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